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    Method and device for performing standby mode in random access memory
    1.
    发明专利
    Method and device for performing standby mode in random access memory 有权
    用于在随机访问存储器中执行待机模式的方法和设备

    公开(公告)号：JP2006309933A

    公开(公告)日：2006-11-09

    申请号：JP2006125982

    申请日：2006-04-28

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： SEITZ HELMUT ,  MENKE MANFRED

    IPC: G11C11/407 ,  G06F1/26 ,  G11C11/403

    CPC classification number: G11C11/406 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067

    Abstract: PROBLEM TO BE SOLVED: To perform efficient power source control while preventing a malfunction in a memory device provided with a low power consumption mode. SOLUTION: The memory device includes a power source system having many power source devices for supplying voltage or current to the memory device, a controller for supplying, into the power source system, a state control signal to instruct the power source devices to be in an active state or a standby state, and a self-refresh oscillator for generating a self-refresh clock signal with a suitable cycle for refreshing memory cells of the memory device. The controller uses the self-refresh clock signal, and delays transition of the state control signal from the active state to the standby state, relatively to the state change corresponding to at least one external signal receiving from the memory device. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：为了在防止具有低功耗模式的存储器件中的故障的同时进行高效的电源控制。 解决方案：存储器件包括具有用于向存储器件提供电压或电流的许多电源装置的电源系统，用于向电源系统提供状态控制信号以指示电源装置 处于活动状态或待机状态，以及自刷新振荡器，用于产生具有适当周期的自刷新时钟信号，用于刷新存储器件的存储单元。 控制器使用自刷新时钟信号，并且将状态控制信号从活动状态转移到待机状态，相对于与从存储器件接收的至少一个外部信号相对应的状态改变。 版权所有（C）2007，JPO＆INPIT

    Transistor voltage level converter circuit for memory decoding circuits has input and output lines and outputs voltage level lower than low state and voltage level higher than high state
    3.
    发明专利
    Transistor voltage level converter circuit for memory decoding circuits has input and output lines and outputs voltage level lower than low state and voltage level higher than high state 未知

    公开(公告)号：DE10216909C1

    公开(公告)日：2003-10-09

    申请号：DE10216909

    申请日：2002-04-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MENKE MANFRED

    IPC: G11C8/08 ,  H03K3/356 ,  H03K17/10 ,  H03K19/0175

    Abstract: The circuit outputs voltage levels lower than the low state and higher than the high state. Two transistors of a first conductivity type have first connections connected to a supply voltage higher than a positive supply voltage. A negative supply voltage is connected to a third transistor of a second type. Fourth and fifth transistors of the second type have first connections connected to a voltage lower than the negative supply voltage. The circuit has input and output lines and outputs a voltage level lower than the low state and a voltage level higher than the high state. First and second transistors (P1,P2) of a first conductivity type have first connections connected to a supply voltage (VPP) higher than a positive supply voltage (VDD). A negative supply voltage (VSS) is connected to a third transistor (N3) of a second conductivity type and fourth and fifth transistors (N1,N2) of the second type have first connections connected to a low voltage lower (VWL) than the negative supply voltage.

    4.
    发明专利
    未知

    公开(公告)号：DE59903253D1

    公开(公告)日：2002-12-05

    申请号：DE59903253

    申请日：1999-04-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MENKE MANFRED ,  PLAN MANFRED

    IPC: G11C29/04 ,  G06F11/20 ,  G11C29/00

    Abstract: A memory configuration is divided into memory blocks and allows a flexible access to redundant memory locations by using both, redundant column lines and redundant row lines of a particular memory block to repair defects of another memory block. Thus more defects can be repaired in the other memory block than there are redundant memory locations present in the other memory block. A method of accessing redundant memory locations is also provided. The memory configuration and the method of accessing redundant memory locations can be used in all memory architectures that write or read one or more bits of information per address in a parallel manner.

    6.
    发明专利
    未知

    公开(公告)号：DE59608121D1

    公开(公告)日：2001-12-13

    申请号：DE59608121

    申请日：1996-08-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MENKE MANFRED

    IPC: G06F7/02 ,  G06F7/24 ,  G06F9/44 ,  G06N7/02 ,  G06N7/04

    Abstract: An ordering method for ranking membership function values (Wi) of linguistic input values (LWEi) in a fuzzy logic processor is presented The steps of the method are: a) within the time of one processor clock, successively reading the membership function values (Wi) into holding elements (L1 . . . L4) and, after every reading, outputs of the holding elements are through-connected onto outputs (A . . . D) of a selector (SC) as determined by a selection signal (SEL); b) comparing the signals at the outputs (A . . . D) of the selector in comparators (C1,C2,C3) and generating control signals (S1 . . . S3) for a unit (SELC) which in turn generates the new selection signal (SEL); and c) writing pointers (MAX, MAX', MAX'', MIN', MIN) into position registers (P1 . . . P5) with the assistance of the control signals (S1 . . . S3) such that the pointers enable a ranked access to the membership function values (Wi) in the holding elements (L1 . . . L4).

    7.
    发明专利
    未知

    公开(公告)号：DE10245546B3

    公开(公告)日：2004-05-13

    申请号：DE10245546

    申请日：2002-09-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： JAKOBS ANDREAS ,  JANIK THOMAS ,  MENKE MANFRED ,  PLAETTNER ECKEHARD

    IPC: G11C11/406 ,  G11C7/24 ,  G11C11/4076

    Abstract: A psuedostatic memory circuit is selected by a memory selection signal. A control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.

    9.
    发明专利
    未知

    公开(公告)号：DE102004001578A1

    公开(公告)日：2005-08-11

    申请号：DE102004001578

    申请日：2004-01-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MENKE MANFRED

    IPC: G01R19/165 ,  H01L23/58 ,  H03K17/22 ,  H03L7/00

    Abstract: An integrated circuit comprises an input for receiving a supply voltage, a field-effect transistor with a gate which is connected to the input in such a manner that the gate voltage present at the gate is a function of the supply voltage, a voltage source for generating a reference voltage which is connected to the input for receiving the supply voltage, a device for determining whether the gate voltage of the field effect transistor exceeds a turn-on voltage of the field-effect transistor, and a device for generating a ready signal which indicates that the supply voltage is high enough for performing functions of the integrated circuit, the device for generating being constructed for generating the ready signal when the gate voltage of the field-effect transistor exceeds the turn-on voltage of the field-effect transistor. The integrated circuit is characterized by the fact that a device for detecting the reference voltage generated by the voltage source is provided and the device for generating the ready signal is also constructed for generating the ready signal only when the reference voltage lies within a predetermined interval.

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