公开(公告)号：DE10127371A1

公开(公告)日：2002-12-12

申请号：DE10127371

申请日：2001-06-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ORDONEZ ESTHER VEGA

IPC: G11C7/06 ,  G11C7/18

Abstract: The arrangement has several memory sectors (6) containing memory cells (8), global bit lines (4) and read amplifiers (1), each for connection via a data bus (2) to a global bit lines. The sectors in each cell can be connected via a local bit line to the global bit line. The read amplifiers are combined into several groups; the amplifiers in each group can be connected via a data bus associated with the group to a corresponding global bit line.

公开(公告)号：DE10053956B4

公开(公告)日：2006-01-19

申请号：DE10053956

申请日：2000-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ORDONEZ ESTHER VEGA ,  KERN THOMAS

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/28

Abstract: A sense amplifier for nonvolatile memories includes a first line path (precharging path) having a first transistor and a third transistor connected in series with the bit line for a memory cell that is to be read. The sense amplifier also includes a second line path (reading path), running parallel to the first line path, in which a transistor diode and a fourth transistor are connected in series with the bit line. The gates of the third transistor and of the fourth transistor are at the same potential, in particular, are connected to one another.

公开(公告)号：DE10113239C1

公开(公告)日：2002-08-22

申请号：DE10113239

申请日：2001-03-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ORDONEZ ESTHER VEGA ,  KERN THOMAS ,  DAAK MATTHIAS VON

IPC: G11C16/28 ,  G11C16/26

Abstract: The invention relates to an evaluation circuit for reading out the information stored in a memory cell, the current (read-out current) carried on a bit line (3) being assessed, the evaluation circuit (10) comprising a bit line decoder (2) and a precharge and converter circuit (4). In order to reduce the read-out duration particularly in the case of large scale integrated memory cells (1), a current source (6) is provided, which increases the read-out current (Imeas) by an offset current (Ioff).

公开(公告)号：DE10053956A1

公开(公告)日：2002-05-23

申请号：DE10053956

申请日：2000-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ORDONEZ ESTHER VEGA ,  KERN THOMAS

IPC: G11C16/28 ,  G11C16/26 ,  G11C7/00

Abstract: A sense amplifier for nonvolatile memories includes a first line path (precharging path) having a first transistor and a third transistor connected in series with the bit line for a memory cell that is to be read. The sense amplifier also includes a second line path (reading path), running parallel to the first line path, in which a transistor diode and a fourth transistor are connected in series with the bit line. The gates of the third transistor and of the fourth transistor are at the same potential, in particular, are connected to one another.