公开(公告)号：DE10356958A1

公开(公告)日：2004-06-24

申请号：DE10356958

申请日：2003-12-05

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： MCSTAY IRENE ,  PARKINSON PORSHIA SHANE

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/205 ,  H01L21/285 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: A method and structure for increasing the area and capacitance of both trench and planar integrated circuit capacitors uses Si nodules deposited on a thin dielectric seeding layer that is absorbed during subsequent thermal processing, thereby avoiding a high resistance layer in the capacitor.

公开(公告)号：DE10341576B4

公开(公告)日：2007-04-19

申请号：DE10341576

申请日：2003-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AKATSU HIROYUKI ,  GLUSCHENKOV OLEG ,  PARKINSON PORSHIA SHANE ,  RAMACHANDRAN RAVIKUMAR ,  SETTLEMYER KENNETH T ,  TEWS HELMUT

IPC: H01L21/8242 ,  H01L21/20

Abstract: Microelectronic structure is manufactured by: (i) forming set of openings in surface of substrate (10); (ii) forming film stack having layers on each sidewall of openings; (iii) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (iv) thermally nitriding silicon layer on upper portion of structure. Fabrication of microelectronic structure comprises: (a) forming set of openings in surface of substrate; (b) forming film stack having layers on each sidewall of openings; (c) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (d) thermally nitriding silicon layer on upper portion of structure to form nitrided silicon layer having first thickness limited through reaction kinetics and less than barrier thickness. The openings have sidewalls that extend to a common bottom wall. The layers include nitride diffusion barrier layer having a barrier thickness and silicon layer deposited after the barrier layer.

公开(公告)号：DE10341576A1

公开(公告)日：2004-03-18

申请号：DE10341576

申请日：2003-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AKATSU HIROYUKI ,  GLUSCHENKOV OLEG ,  PARKINSON PORSHIA SHANE ,  RAMACHANDRAN RAVIKUMAR ,  SETTLEMYER KENNETH T ,  TEWS HELMUT

IPC: H01L21/20 ,  H01L21/8242

Abstract: Microelectronic structure is manufactured by: (i) forming set of openings in surface of substrate (10); (ii) forming film stack having layers on each sidewall of openings; (iii) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (iv) thermally nitriding silicon layer on upper portion of structure. Fabrication of microelectronic structure comprises: (a) forming set of openings in surface of substrate; (b) forming film stack having layers on each sidewall of openings; (c) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (d) thermally nitriding silicon layer on upper portion of structure to form nitrided silicon layer having first thickness limited through reaction kinetics and less than barrier thickness. The openings have sidewalls that extend to a common bottom wall. The layers include nitride diffusion barrier layer having a barrier thickness and silicon layer deposited after the barrier layer.