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    DUAL GATE OXIDE PROCESS FOR UNIFORM OXIDE THICKNESS
    2.
    发明申请
    DUAL GATE OXIDE PROCESS FOR UNIFORM OXIDE THICKNESS 审中-公开
    用于均匀氧化物厚度的双栅氧化工艺

    公开(公告)号：WO0237561A2

    公开(公告)日：2002-05-10

    申请号：PCT/US0143859

    申请日：2001-11-06

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： TEWS HELMUT ,  WEYBRIGHT MARY ,  KUDELKA STEPHAN ,  GLUSCHENKOV OLEG ,  HEGDE SURI

    IPC: H01L21/265 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/51

    CPC classification number: H01L21/28185 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/823462 ,  H01L27/10873 ,  H01L29/518 ,  Y10S438/981

    Abstract: A process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising:a) growing a sacrificial oxide layer on a substrate;b) implanting a dopant through the sacrificial oxide layer;c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer; d) subjecting the substrate to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface;e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide;f) implanting a second dosage of nitrogen ions through the photoresist;g) stripping the photoresist and the sacrificial oxide layers; and h) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas in the thin and thick oxides.

    Abstract translation: 一种用于形成用于高性能DRAM系统或逻辑电路的改进的氧化物厚度均匀性的双栅极氧化物的方法，包括：a）在衬底上生长牺牲氧化物层; b）通过所述牺牲氧化物层注入掺杂剂; c） 不存在光致抗蚀剂的氮离子的第一剂量形成氮化硅层; d）对衬底进行快速热退火足够的时间和足够的温度以使氮气扩散到硅/氧化物界面; e）用光致抗蚀剂掩蔽衬底以限定双重氧化物的薄氧化物的位置 栅极氧化物; f）通过光致抗蚀剂注入第二剂量的氮离子; g）剥离光致抗蚀剂和牺牲氧化物层; 和h）通过氧化栅氧化层生长，其特征在于在薄和厚的氧化物中的氮离子注入区域中改善的氧化物厚度均匀性。

    3.
    发明专利
    未知

    公开(公告)号：DE10350354B4

    公开(公告)日：2007-08-16

    申请号：DE10350354

    申请日：2003-10-29

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT

    IPC: H01L21/316 ,  H01L21/314 ,  H01L21/318 ,  H01L21/321 ,  H01L21/336 ,  H01L29/04 ,  H01L29/78

    Abstract: Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.

    4.
    发明专利
    未知

    公开(公告)号：DE102004013928A1

    公开(公告)日：2004-10-28

    申请号：DE102004013928

    申请日：2004-03-22

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： BELYANSKY MICHAEL ,  GLUSCHENKOV OLEG ,  KNORR ANDREAS ,  PARKS CHRISTOPHER

    IPC: H01L21/762 ,  H01L21/316 ,  H01L21/3105 ,  H01L21/8242

    Abstract: A trench isolation structure is formed in a substrate. One or more openings are formed in a surface of the substrate, and a liner layer is deposited at least along a bottom and sidewalls of the openings. A layer of doped oxide material is deposited at least in the openings, and the substrate is annealed to reflow the layer of doped oxide material. Only a portion near the surface of the substrate is removed from the layer of doped oxide material in the opening. A cap layer is deposited atop a remaining portion of the layer of doped oxide material in the opening.

    5.
    发明专利
    未知

    公开(公告)号：DE10341576B4

    公开(公告)日：2007-04-19

    申请号：DE10341576

    申请日：2003-09-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： AKATSU HIROYUKI ,  GLUSCHENKOV OLEG ,  PARKINSON PORSHIA SHANE ,  RAMACHANDRAN RAVIKUMAR ,  SETTLEMYER KENNETH T ,  TEWS HELMUT

    IPC: H01L21/8242 ,  H01L21/20

    Abstract: Microelectronic structure is manufactured by: (i) forming set of openings in surface of substrate (10); (ii) forming film stack having layers on each sidewall of openings; (iii) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (iv) thermally nitriding silicon layer on upper portion of structure. Fabrication of microelectronic structure comprises: (a) forming set of openings in surface of substrate; (b) forming film stack having layers on each sidewall of openings; (c) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (d) thermally nitriding silicon layer on upper portion of structure to form nitrided silicon layer having first thickness limited through reaction kinetics and less than barrier thickness. The openings have sidewalls that extend to a common bottom wall. The layers include nitride diffusion barrier layer having a barrier thickness and silicon layer deposited after the barrier layer.

    6.
    发明专利
    未知

    公开(公告)号：DE102004001099A1

    公开(公告)日：2004-07-22

    申请号：DE102004001099

    申请日：2004-01-05

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： BELYANSKY MICHAEL ,  GLUSCHENKOV OLEG ,  KNORR ANDREAS

    IPC: C23C8/36 ,  H01L21/316

    Abstract: A method of oxidizing a substrate having area of about 30,000 mm 2 or more. The surface is preferably comprised of silicon-containing materials, such as silicon, silicon germanium, silicon carbide, silicon nitride, and metal silicides. A mixture of oxygen-bearing gas and diluent gas normally non-reactive to oxygen, such as Ne, Ar, Kr, Xe, and/or Rn are ionized to create a plasma having an electron density of at least about 1 e12 cm -3 and containing ambient electrons having an average temperature greater than about 1 eV. The substrate surface is oxidized with energetic particles, comprising primarily atomic oxygen, created in the plasma to form an oxide film of substantially uniform thickness. The oxidation of the substrate takes place at a temperature below about 700° C., e.g., between about room temperature, 20° C., and about 500° C.

    10.
    发明专利
    未知

    公开(公告)号：DE10246306A1

    公开(公告)日：2003-04-30

    申请号：DE10246306

    申请日：2002-10-04

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： CHUDZIK MICHAEL ,  GLUSCHENKOV OLEG ,  JAMMY RAJARAO ,  SCHROEDER UWE ,  TEWS HELMUT

    IPC: H01L21/316 ,  H01L21/321 ,  H01L21/8242 ,  H01G4/06

    Abstract: An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.

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