公开(公告)号：JP2002223160A

公开(公告)日：2002-08-09

申请号：JP2001340958

申请日：2001-11-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POLNEY JENS

IPC: G11C11/409 ,  G11C5/14 ,  G11C7/10 ,  G11C7/20 ,  H03K17/22 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0944

Abstract: PROBLEM TO BE SOLVED: To provide a circuit device that has a small occupied area and a supply voltage that is operated safely and generated internally at a manufacture state of an integrated circuit. SOLUTION: This invention provides the circuit device that has a terminal to which an external supply voltage is applied, a voltage generator having a terminal to pick up an internal voltage different from the external supply voltage and being energized by the external supply voltage, a reference level terminal, switching stage, a control circuit generating a pre-charge signal and an internal supply voltage.

公开(公告)号：JP2001236264A

公开(公告)日：2001-08-31

申请号：JP2001009222

申请日：2001-01-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POLNEY JENS

IPC: G06F12/06 ,  G06F12/00 ,  G06F12/04 ,  G06F12/16 ,  G11C7/10

Abstract: PROBLEM TO BE SOLVED: To operate a writing and reading memory alternately in one memory operation mode and an interleave multi-memory operation mode by reducing a required space to be occupied by a control element on a chip to the minimum. SOLUTION: A control line 45 connecting a control logic 33 to each memory cell of a cell field 31 is provided, and a selection signal sequence for an interleave multi-memory operation is supplied to the control line 45 when an operation mode signal 46 indicates an interleave multi-memory operation mode, and a mask signal sequence for a writing enable operation is supplied to the control line 45 when the operation mode signal 46 indicates one memory operation mode.

公开(公告)号：US6363017B2

公开(公告)日：2002-03-26

申请号：US76646501

申请日：2001-01-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POLNEY JENS

IPC: G06F12/06 ,  G06F12/00 ,  G06F12/04 ,  G06F12/16 ,  G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1045 ,  G11C7/1006

Abstract: In a random access memory, a sequence of selection signals for a combined multi-memory operating functionality is supplied on control lines which connect the control logic to each memory cell in a cell field when the memory is in a combined multi-memory operating mode, and a sequence of selection signals for the write enable functionality is supplied when the memory is in the single-memory operating mode.

Abstract translation: 在随机存取存储器中，当存储器处于组合的多存储器操作模式时，在控制线路上提供用于组合的多存储器操作功能的选择信号序列，所述控制线路将控制逻辑连接到单元区域中的每个存储器单元， 并且当存储器处于单存储器操作模式时，提供用于写入使能功能的选择信号的序列。

公开(公告)号：DE10002831C2

公开(公告)日：2002-01-03

申请号：DE10002831

申请日：2000-01-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POLNEY JENS

IPC: G01R31/319 ,  G01R31/3193 ,  G01R31/3177 ,  H01L21/66 ,  G11C29/00

Abstract: A method for testing electronic components includes the step of outputting test output data for the tested electronic components on a test board without activating individual scan lines or individual scan signals. Starting from a first activated electronic component successively the following electronic components are activated one after another by passing an activation signal from electronic component to electronic component. A device for testing electronic components is also provided.

公开(公告)号：DE50100644D1

公开(公告)日：2003-10-23

申请号：DE50100644

申请日：2001-10-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POLNEY JENS

IPC: G11C11/409 ,  G11C5/14 ,  G11C7/10 ,  G11C7/20 ,  H03K17/22 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0944

Abstract: In integrated circuits with internally generated supply voltages, during the run-up of the internal voltage generators, unintentionally high currents can arise through switching stages connected to the internal supply voltage. A control circuit provides for the initialization of the switching stages during power-up. The control circuit contains an inverter that, in signal terms, can be driven by a precharge signal and, on the supply voltage side, is connected to the internal supply voltage via respective transistors. During power-up, the transistors are switched off and then switched on. The precharge signal is forwarded to the switching stage via a further inverter.

公开(公告)号：DE10244516B4

公开(公告)日：2006-11-16

申请号：DE10244516

申请日：2002-09-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE ,  SZCZYPINSKI KAZIMIERZ ,  POLNEY JENS

IPC: H03K19/0175 ,  G11C7/06 ,  H03K19/00 ,  H03K19/0185

Abstract: An integrated circuit, in particular an integrated memory circuit, has an input circuit for the purpose of receiving a signal. The input circuit has an activation input for an activation signal in order to activate the input circuit, in a manner dependent on the activation signal, for the purpose of receiving signals.

公开(公告)号：DE10055242C1

公开(公告)日：2002-02-21

申请号：DE10055242

申请日：2000-11-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POLNEY JENS

IPC: G11C11/409 ,  G11C5/14 ,  G11C7/10 ,  G11C7/20 ,  H03K17/22 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0944

Abstract: The circuit has a terminal (33) receiving an external supply voltage (VEXT), used for operation of a voltage generator (3) having an internal voltage supply terminal (31), used for operation of a switch stage (1) having at least 2 transistors (10,11) with their current paths connected in series. One of the transistors is controlled by a logic signal (Q), the other controlled by a bias signal (ENB) provided by a control circuit (2) with a first inverter (21) using complementary transistors, coupled to a second inverter (25) with a bias signal output.

公开(公告)号：DE10002831A1

公开(公告)日：2001-08-09

申请号：DE10002831

申请日：2000-01-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POLNEY JENS

IPC: G01R31/319 ,  G01R31/3193 ,  G01R31/3177 ,  H01L21/66 ,  G11C29/00

Abstract: A method for testing electronic components includes the step of outputting test output data for the tested electronic components on a test board without activating individual scan lines or individual scan signals. Starting from a first activated electronic component successively the following electronic components are activated one after another by passing an activation signal from electronic component to electronic component. A device for testing electronic components is also provided.

公开(公告)号：DE10002130A1

公开(公告)日：2001-08-02

申请号：DE10002130

申请日：2000-01-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POLNEY JENS

IPC: G06F12/06 ,  G06F12/00 ,  G06F12/04 ,  G06F12/16 ,  G11C7/10 ,  G11C7/00 ,  G11C11/409

Abstract: The method involves placing a series of selection signals for limited multiple memory mode on control lines (45) connecting control logic (33) to memory cells of a cell field (31) if a mode signal (46) indicates limited multiple memory mode. A series of mask signals is applied for write enabling functionality if the mode signal indicates single memory mode.

公开(公告)号：DE102004055674A1

公开(公告)日：2006-05-24

申请号：DE102004055674

申请日：2004-11-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL FLORIAN ,  POLNEY JENS

IPC: G11C7/14

Abstract: A device for writing/reading a memory cell (1) has first (5) and second (6) devices for influencing a selecting transistor's (2) threshold voltage against the effects from a surrounding temperature. The first device is an electric voltage generator (5) for attaching voltage to the selecting transistor's substrate trough (4). An independent claim is also included for a method for writing/reading a memory cell in a semiconductor device.