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    4.
    发明专利
    未知

    公开(公告)号：DE10051164B4

    公开(公告)日：2007-10-25

    申请号：DE10051164

    申请日：2000-10-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHAEFER ANDRE ,  GALL MARTIN

    IPC: G11C11/4093 ,  G11C7/10 ,  G11C11/4096

    Abstract: A method for masking DQ bits that are input into a semiconductor memory by a memory controller is described. In this case, the bits to be masked are provided with an increased level and therefore cannot be read into the semiconductor memory due to the increased voltage level which functions as a deactivating voltage level.

    5.
    发明专利
    未知

    公开(公告)号：DE102005040109A1

    公开(公告)日：2007-03-15

    申请号：DE102005040109

    申请日：2005-08-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WALLNER PAUL ,  SCHAEFER ANDRE ,  GREGORIUS PETER

    IPC: G11C7/10

    Abstract: A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip in signal frames in correspondence with a predetermined protocol. In a receive signal path within the semiconductor memory chip, a frame decoder for decoding the signal frames is arranged following a receiving interface device, and between the frame decoder and a memory core, an intermediate storage device is arranged which has a cell array including a multiplicity of memory cells, and an addressing and selector circuit to which address signals decoded by the frame decoder from command and/or write signal frames supplied by the memory controller are applied, for addressing the cell array and for selecting the write data to be written into the cell array and to be read out of the cell array.

    Device for producing refresh signal for semiconducting memory device memory cell produces capacitor charging current proportional to difference between temperature dependent and independent currents
    8.
    发明专利
    Device for producing refresh signal for semiconducting memory device memory cell produces capacitor charging current proportional to difference between temperature dependent and independent currents 未知

    公开(公告)号：DE10214101A1

    公开(公告)日：2003-10-23

    申请号：DE10214101

    申请日：2002-03-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHNABEL JOACHIM ,  SCHAEFER ANDRE

    IPC: G11C7/04 ,  G11C11/406 ,  H03K3/0231 ,  G11C11/4076 ,  H03L7/00 ,  H03K3/0232

    Abstract: The device has a capacitor, a differential current source for providing a capacitor charging current with temperature dependent and temperature independent current sources connected together so the current level of the capacitor charging current is proportional to the difference between the temperature dependent and temperature independent currents. A comparator outputs a refresh signal if the capacitor voltage exceeds a reference voltage. The device has a capacitor (C), a differential current source (14) for providing a capacitor charging current for charging the capacitor with temperature dependent and temperature independent current sources that are connected together so that the current level of the capacitor charging current is proportional to the difference between the temperature dependent and temperature independent currents. A comparator (12) outputs a refresh signal if the capacitor voltage (VC) exceeds a reference voltage (VREF). AN Independent claim is also included for the following: an arrangement for implementing the inventive method of producing a refresh signal for a memory cell of a semiconducting memory device, preferably a DRAM memory.

    9.
    发明专利
    未知

    公开(公告)号：DE10154505A1

    公开(公告)日：2003-05-15

    申请号：DE10154505

    申请日：2001-11-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ZUCKERSTAETTER ANDREA ,  SCHAEFER ANDRE

    IPC: G11C5/14 ,  G11C7/04

    Abstract: A memory device includes a memory module, a control unit and a bus connected to the memory module and the control unit. In an accessing operation of the memory module via bus, the control unit applies a first command which causes high power consumption in the memory module, to the memory module via part of the bus only.

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