公开(公告)号：DE102005036288A1

公开(公告)日：2007-02-08

申请号：DE102005036288

申请日：2005-08-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL FLORIAN ,  SCHNEIDER HELMUT

IPC: G01R31/28

Abstract: The probe (31) has a probe tip (32) for contacting a circuit to be tested, and a repeater (34) for isolating the probe tip from a set of signal lines (S 1, S 2, S i). A potential adjacent to the probe tip is transmitted to the signal lines, and a switching device (35) conductively connects the probe tip with one of the signal lines in such a manner that excitation signal applied to one of the signal lines is injectable into the circuit to be tested. An independent claim is also included for a method for operating an active probe.

公开(公告)号：DE10154614C1

公开(公告)日：2003-05-08

申请号：DE10154614

申请日：2001-11-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL FLORIAN

IPC: G01R31/3187 ,  G11C29/48 ,  G11C29/00

公开(公告)号：DE10145727A1

公开(公告)日：2003-04-17

申请号：DE10145727

申请日：2001-09-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL FLORIAN ,  PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G01R31/28 ,  G11C11/401 ,  G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  H01L21/822 ,  H01L27/04 ,  G01R31/3187

Abstract: A test module (30) set up for testing an electronic circuit connects to a wire (38,40) and/or a connector for the electronic circuit. A test control signal (34) is generated, with which the test module in an operating module for the electronic circuit is decoupled from the wire or the connector in such a way that switching currents are avoided in the test module. An Independent claim is also included for a device for reducing power consumption in an electronic circuit.

公开(公告)号：DE102005016597B3

公开(公告)日：2006-06-29

申请号：DE102005016597

申请日：2005-04-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL FLORIAN ,  SCHNEIDER HELMUT

IPC: G11C7/12 ,  G11C11/4074 ,  G11C11/4094

Abstract: The electronic component (10) has first bit line (14) and second bit line (16) coupled with memory cells (12). The first bit line and second bit line are connected to controllable resistor (36). The electrical resistance of the resistor is thus controllable by applying pre-determined resistance value. The pre-determined second resistance value is greater than the pre-determined first resistance value. An independent claim is also included for the method for operation of electronic component.

公开(公告)号：DE10065663A1

公开(公告)日：2002-07-11

申请号：DE10065663

申请日：2000-12-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL FLORIAN ,  ROEHNER MICHAEL ,  KASKO IGOR ,  NAGEL NICOLAS

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/00 ,  H01L23/26 ,  H01L21/283 ,  H01L27/108

Abstract: Semiconductor switching arrangement comprises a semiconductor substrate (18); a contact element (14) formed in one region on the substrate; and a contact region (16). Edge regions, side regions, boundary layers or boundary surfaces are formed in a region of the contact region for receiving components. Diffusion of the components during processing and/or operation is reduced along the edge regions, side regions, boundary layers or boundary surfaces. An Independent claim is also included for a process for the production of the semiconductor switching arrangement. Preferred Features: A barrier region (15) is formed between the contact element and the contact region to form a partial screen.

公开(公告)号：DE102006026970A1

公开(公告)日：2007-12-13

申请号：DE102006026970

申请日：2006-06-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEWER FALK ,  SICHERT CHRISTIAN ,  SCHNABEL FLORIAN

IPC: G11C11/4093

Abstract: The memory has a memory layer (100) with memory cells to store data. A control circuit (40) controls a memory circuit (20) e.g. latch, in such a manner that intermediately stored data is outputted to a side or to another side of a clock signal from the memory circuit during write access and the intermediately stored data is outputted to a third side and supplied to the memory layer. The control circuit controls the memory circuit in such a manner that the data supplied from the memory layer and the data are stored in the memory circuit during read access. An independent claim is also included for a method of operating an integrated semiconductor memory.

公开(公告)号：DE102006024215A1

公开(公告)日：2007-10-31

申请号：DE102006024215

申请日：2006-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL FLORIAN ,  FISCHER HELMUT

IPC: G11C29/52 ,  G06F11/00 ,  G06F12/04

Abstract: The method involves simultaneously selecting a number of data bits corresponding to a data item width from memory cells (1) of a cell field (2) of a semiconductor memory device, where the selected data bits are combined in groups on a data bus with another data item width that is small when compared to the former data item width. The data bits are temporally outputted in a distributed manner to several successive edges of a clock signal, where bit lines of memory cells are activated by a common column select line. An independent claim is also included for a semiconductor memory device with a cell field.

公开(公告)号：DE10216874A1

公开(公告)日：2003-07-10

申请号：DE10216874

申请日：2002-04-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL FLORIAN ,  FRANKOWSKY GERD

IPC: H01L23/544

Abstract: A process for laying down information on a semiconductor chip comprises forming a wafer level package with isolation and contact elements (32) to bondpads (31) for testing. An individual ID is integrated into each chip which can be read optically after the chips have been individualized. An Independent claim is also included for a semiconductor chip as above.

公开(公告)号：DE102004059723A1

公开(公告)日：2006-06-14

申请号：DE102004059723

申请日：2004-12-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL FLORIAN ,  SCHNEIDER HELMUT

IPC: G11C7/18 ,  G11C11/407 ,  G11C11/4097 ,  H01L27/108

Abstract: A memory component comprises bitlines (11-29) with which memory cells (71-78,81-88) are arranged and a row of read amplifiers (41-44) each connected to two bitlines. A bitline connected to a first read amplifier is next to a bitline connected to a second read amplifier in the row.

公开(公告)号：DE10151609A1

公开(公告)日：2003-04-30

申请号：DE10151609

申请日：2001-10-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL FLORIAN ,  PFEIFFER JOHANN

IPC: G11C29/14 ,  G11C29/00

Abstract: Inputs (TE) are fitted at one side of SPC, with their numbers exceeding that of conductive tracks. A coder (ENC) has its input coupled to the inputs, and its output to one end of conductive tracks, also located at one side of SPC.A decoder (DEC) has its input coupled to the other end of conductive tracks, and its output to the circuit outputs (TA), while being fitted at the other side of SPC. Preferably a flank detector (SD) is incorporated between circuit inputs and coder.