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公开(公告)号:DE10331571A1
公开(公告)日:2005-02-03
申请号:DE10331571
申请日:2003-07-11
Applicant: INFINEON TECHNOLOGIES AG
Inventor: PAULUS CHRISTIAN , PRAKASH RAMESH , BREDERLOW RALF
Abstract: The integrated circuit device has at least one NMOS field effect transistor (T(N)1,T(N)2) and at least one PMOS field effect transsitor (T(P)), each having 2 channel terminals and a gate terminal and connected in series, their gate voltages (V(GN),V(GP) selected so that at least one of the series transistors is below its threshold voltage for providing an effective resistance (R) across the series circuit.