公开(公告)号：DE10328594B4

公开(公告)日：2008-04-24

申请号：DE10328594

申请日：2003-06-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAIPRAKASH VENKATACHALAN C ,  RANADE RAJIV

IPC: H01L27/108 ,  H01L21/8242

Abstract: Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.

公开(公告)号：DE69929266D1

公开(公告)日：2006-03-30

申请号：DE69929266

申请日：1999-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MICHAELIS ALEXANDER ,  RANADE RAJIV ,  FLIETNER BERTRAND

IPC: H01L21/302 ,  H01L29/94 ,  H01L21/02 ,  H01L21/30 ,  H01L21/3065 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: A vertical trench in a silicon wafer for use in forming the storage capacitor of a DRAM is etched by reactive ion etching in a manner to have a profile that has multiple waists. This profile is obtained by varying the rate of flow of coolant in the base member on which the silicon wafer is supported during the reactive ion etching to vary the temperature of the silicon wafer during the etching. Alternatively, the multiple waists are achieved by either by varying the ratio of the different gases in the etching chamber or the total gas pressure in the chamber.

公开(公告)号：DE10320944A1

公开(公告)日：2003-11-27

申请号：DE10320944

申请日：2003-05-09

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： MATHAD GANGADHARA ,  PANDA SIDDHARTHA ,  RANADE RAJIV

IPC: H01L21/3065 ,  H01L21/8242

Abstract: A method of fabricating a high aspect ratio deep trench in a semiconductor substrate comprising reducing the formation of a passivation film during the etching of the trench by including a first step of contacting the substrate in which the deep trench is to be formed with a fluorine poor or low concentration of a fluorine gas in the plasma of etchant gases for etching the high aspect ratio deep trench, followed by a second step of increasing the concentration of the fluorine containing gas to create a fluorine-rich plasma while lowering the chamber pressure of the reactor and RF power. Preferably, the second step is introduced periodically during the etching of a deep trench in an alternating manner.

公开(公告)号：DE10328594A1

公开(公告)日：2004-01-29

申请号：DE10328594

申请日：2003-06-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PRAIKASH JAI VENKATACHALAN C ,  RANADE RAJIV

IPC: H01L21/8242 ,  H01L27/108

Abstract: Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.

公开(公告)号：DE69929266T2

公开(公告)日：2006-08-17

申请号：DE69929266

申请日：1999-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MICHAELIS ALEXANDER ,  RANADE RAJIV ,  FLIETNER BERTRAND

IPC: H01L21/302 ,  H01L29/94 ,  H01L21/02 ,  H01L21/30 ,  H01L21/3065 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: A vertical trench in a silicon wafer for use in forming the storage capacitor of a DRAM is etched by reactive ion etching in a manner to have a profile that has multiple waists. This profile is obtained by varying the rate of flow of coolant in the base member on which the silicon wafer is supported during the reactive ion etching to vary the temperature of the silicon wafer during the etching. Alternatively, the multiple waists are achieved by either by varying the ratio of the different gases in the etching chamber or the total gas pressure in the chamber.