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公开(公告)号：DE102004019366A1
公开(公告)日：2005-11-17
申请号：DE102004019366
申请日：2004-04-21
Applicant: INFINEON TECHNOLOGIES AG
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公开(公告)号：DE10360470A1
公开(公告)日：2005-07-21
申请号：DE10360470
申请日：2003-12-22
Applicant: INFINEON TECHNOLOGIES AG
Inventor： LI PUMA GIUSEPPE , WIESBAUER ANDREAS , SANDNER CHRISTOPH , VAN WAASEN STEFAN , GREWING CHRISTIAN , FRIEDRICH MARTIN , WINTERBERG KAY
Abstract: A method and an arrangement for processing a received signal which comprises phase-shift modulated or amplitude-quadrature modulated part-signals which are transmitted in a plurality of different frequency bands, wherein the received signal is processed in a plurality of stages in succession, by multiplying all the input signals to each of the stages by two mutually orthogonal signals in each case to form two intermediate signals in each case, wherein the intermediate signals from one stage in each case act as the input signals to whichever is the succeeding stage in the particular case and the received signal acts as the input signal to the first stage, and wherein an in-phase and/or an quadrature component of the individual part-signals in the different frequency bands are determined from the intermediate signals from the last stage. Parallel, simultaneous reception of a plurality of frequency bands can be implemented relatively easily in this way.
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公开(公告)号：DE102015103715B4
公开(公告)日：2021-06-10
申请号：DE102015103715
申请日：2015-03-13
Applicant: INFINEON TECHNOLOGIES AG
Inventor： AGOSTINELLI MATTEO , SANDNER CHRISTOPH
Abstract: Schaltkreis umfassend:einen Gleichrichter (34), welcher ausgestaltet ist, eine Gleichstromausgabe aus einer Wechselstromeingabe gleichzurichten, wobei der Gleichrichter (34) mindestens ein Niederseitenelement (Low-Side-Element) (22), mindestens ein Hochseitenelement (High-Side-Element) (20) und mindestens ein Schaltelement (54), welches parallel zu dem mindestens einen Niederseitenelement (Low-Side-Element) (22) angeordnet ist, umfasst;eine Erfassungseinheit (38), welche ausgestaltet ist, einen Spannungspegel der Gleichstromausgabe zu erfassen;eine Steuereinheit (30), welche ausgestaltet ist, den Gleichrichter (34) basierend auf dem Spannungspegel der Gleichstromausgabe durch Aktivieren oder Deaktivieren des mindestens einen Niederseitenelements (Low-Side-Element) (22) zu steuern, indem der Gleichrichter (34) gesteuert wird, um:die Gleichstromausgabe aus der Wechselstromeingabe gleichzurichten, wenn der Spannungspegel der Gleichstromausgabe keinen Überspannungszustand an dem Schaltkreis (4) anzeigt; undeinen Strom von der Wechselstromeingabe gegen Masse abzuleiten, wenn der Spannungspegel der Gleichstromausgabe den Überspannungszustand anzeigt, indem im Fall des Überspannungszustands zumindest das mindestens eine Schaltelement (54) aktiviert wird, ohne zu ändern, dass das mindestens eine Niederseitenelement (Low-Side-Element) (22) aktiviert oder deaktiviert wird.
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公开(公告)号：DE50105372D1
公开(公告)日：2005-03-24
申请号：DE50105372
申请日：2001-05-08
Applicant: INFINEON TECHNOLOGIES AG
Inventor： DA DALT NICOLA , SANDNER CHRISTOPH
Abstract: A digital phase-locked loop with a digitally controlled oscillator is disclosed. The phase difference between a reference phase and a phase derived from the output phase of the oscillator is determined by a phase detector device and converted into a corresponding digital set value. The digital set value from the phase detector device is fed through a digital filter, to the digitally controlled oscillator, for the corresponding setting of the output phase thereof. By means of the above architecture any digital loop filter may be used.
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公开(公告)号：DE10238029A1
公开(公告)日：2004-03-04
申请号：DE10238029
申请日：2002-08-20
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SANDNER CHRISTOPH , DA DALT NICOLA
Abstract: The PLL (10) has several VCOs (12,14) for generating output frequency in different frequency ranges. Between two VCOs and loop filter (16) is incorporated at least one driver circuit (18,20) for limiting capacitive load affecting loop filter.Typically at least one driver circuit is located in front of input of each VCO. The driver circuit may contain a driver circuit stage assembly and source follower and fed back operational amplifier. One VCO may include a varactor and inductance as oscillating element. Independent claims are included for PLL application in an electric and optical transceiver circuit.
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Patent Agency Ranking
公开(公告)号：DE102015103715A1
公开(公告)日：2015-09-17
申请号：DE102015103715
申请日：2015-03-13
Applicant: INFINEON TECHNOLOGIES AG
Inventor： AGOSTINELLI MATTEO , SANDNER CHRISTOPH
Abstract: Ein Schaltkreis (4) wird beschrieben, welcher einen Gleichrichter (34), welcher ausgestaltet ist, eine Gleichstromausgabe aus einer Wechselstromeingabe gleichzurichten, eine Erfassungseinheit (38), welche ausgestaltet ist, einen Spannungspegel der Gleichstromausgabe zu erfassen, und eine Steuereinheit (30), welche ausgestaltet ist, den Gleichrichter (34) basierend auf dem Spannungspegel der Gleichstromausgabe zu steuern, aufweist. Die Steuereinheit (30) ist ausgestaltet, die Gleichrichterausgabe zu steuern, indem zumindest der Gleichrichter (34) angesteuert wird, die Gleichstromausgabe aus der Wechselstromeingabe gleichzurichten, wenn der Spannungspegel der Gleichstromausgabe keinen Überspannungszustand an dem Schaltkreis (4) anzeigt. Zusätzlich ist die Steuereinheit (30) ausgestaltet, den Gleichrichter (34) basierend auf dem Spannungspegel der Gleichstromausgabe zu steuern, indem zumindest der Gleichrichter (34) gesteuert wird, einen Strom von der Wechselstromeingabe abzuleiten, wenn der Spannungspegel der Gleichstromausgabe den Überspannungszustand anzeigt.
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公开(公告)号：DE102004019366B4
公开(公告)日：2006-05-04
申请号：DE102004019366
申请日：2004-04-21
Applicant: INFINEON TECHNOLOGIES AG
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公开(公告)号：DE102004021155B3
公开(公告)日：2005-12-29
申请号：DE102004021155
申请日：2004-04-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GREWING CHRISTIAN , FRIEDRICH MARTIN , WINTERBERG KAY , WAASEN STEFAN VAN , LI PUMA GUISEPPE , WIESBAUER ANDREAS , SANDNER CHRISTOPH
Abstract: A traveling wave amplifier comprises a first normally off MOS transistor having a drain, source and gate terminal. The drain terminal is connected to a node of a drain line, which is connected to a first supply voltage potential via a connecting resistor. The gate terminal is connected to a node of a gate line, onto which an input signal is coupled. The source terminal is coupled to a second supply voltage potential via a first resistor. The traveling wave amplifier also comprises at least one second normally off MOS transistor. In addition, the traveling wave amplifier further comprises a normally off bias MOS transistor. The normally off bias MOS transistor forms a current mirror with at least one of the second normally off MOS transistors. An output signal of the traveling wave amplifier is tapped off on the drain line.
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公开(公告)号：DE102004013217A1
公开(公告)日：2005-10-13
申请号：DE102004013217
申请日：2004-03-17
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GREWING CHRISTIAN , FRIEDRICH MARTIN , WINTERBERG KAY , WAASEN STEFAN VAN , WIESBAUER ANDREAS , SANDNER CHRISTOPH , LI PUMA GUISEPPE
Abstract: Programmable difference amplifier (1) has first load (7), first transistor (8) with a first controllable extent and a first gate connection (9) and a first adjustable current source (10). The first load, the first controllable extent and the first adjustable current source are connected in series between first and second supply voltage connections (VDD,VSS), with a second load (11), a second transistor (12), which has a second controllable extent and a second gate connection (13), and a second adjustable current source (14). The second load, the second controllable extent and the second controllable current source are connected in series between the first and second supply voltage connections. At the gate connections (9,13) a differential input signal (IN,INX) is applied. At a first conduit node (16) between the first load and the first controllable extent and at a second conduit node (15) between the second load and the second controllable extent an amplified differential output signal (OUT,OUTX) is applicable. A counter coupling device (17) for the adjustment of the amplification of the differential amplifier has a programmable resistance value and is connected between third and fourth conduit nodes (18,19). The third conduit node is between the first controllable extent of the first transistor and the first adjustable current source. The fourth conduit node is between the controllable extent of the second transistor and the second adjustable current source. To the counter coupling device the programming signal (CTRL) is applied.
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公开(公告)号：DE102004021153B3
公开(公告)日：2005-09-15
申请号：DE102004021153
申请日：2004-04-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GREWING CHRISTIAN , FRIEDRICH MARTIN , WINTERBERG KAY , WAASEN STEFAN VAN , LI PUMA GIUSEPPE , WIESBAUER ANDREAS , SANDNER CHRISTOPH
Abstract: The signal amplifier (8) is tunable so as to operate over a number of narrow channels or signal bands. It has two inputs (15- 1,15-2) connected to bandpass switching networks (16-1,16-2). The networks are connected (17-1,17-2) to NMOSTs (18.1,18.2). Frequency control signals (KW) are transmitted to the bandpass switching networks via connections (11- 1,11-2) leading from the frequency control circuit. The NMOSTs are connected to a cascode stage (23). A switch control logic circuit (34) receives control signals and is connected to groups of switches (31a- 1...31a-N) and (31b-1...31b-N), switching capacitors (30a-1...30a-N) and (30b-1...30b-N) in and out of circuit.
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