公开(公告)号：JP2007110098A

公开(公告)日：2007-04-26

申请号：JP2006247813

申请日：2006-09-13

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： SCHENK ANDRE ,  TEWS HELMUT

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/66477 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7834

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method of which a stress is adjusted for improved performance.
SOLUTION: A gate electrode 104 is electrically insulated from a semiconductor substrate (bulk silicon substrate, SOI layer, or the like) 102. A first side wall spacer 110 is formed along the side wall of the gate electrode 104. A sacrifice side wall spacer is so formed as to adjoin the first side wall spacer 110. The sacrifice side wall spacer and the first side wall spacer 110 cover the semiconductor substrate 102. A flattened layer is formed to cover the semiconductor substrate 102 so that a part of the flattened layer adjoins the sacrifice side wall spacer. The sacrifice side wall spacer is removed, and a recess is formed in the semiconductor substrate 102 by etching. The recess is substantially arranged between the first side wall spacer 110 and a part of the flattened layer. A semiconductor material (SiGe, SiC, or the like) 116 is deposited in the recess.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供调整应力以提高性能的半导体器件及其制造方法。 解决方案：栅电极104与半导体衬底（体硅衬底，SOI层等）102电绝缘。沿着栅电极104的侧壁形成第一侧壁间隔物110.牺牲 侧壁间隔件形成为邻接第一侧壁间隔物110.牺牲侧壁隔离物和第一侧壁隔离物110覆盖半导体衬底102.形成平坦层以覆盖半导体衬底102，使得部分 扁平层与牺牲侧壁间隔物邻接。 除去牺牲侧壁间隔物，通过蚀刻在半导体衬底102中形成凹部。 凹部基本上布置在第一侧壁间隔件110和平坦层的一部分之间。 在凹部中沉积半导体材料（SiGe，SiC等）116。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：SG136860A1

公开(公告)日：2007-11-29

申请号：SG2007018153

申请日：2007-03-12

Applicant: CHARTERED SEMICONDUCTOR MFG ,  SAMSUNG ELECTRONICS CO LTD ,  INFINEON TECHNOLOGIES AG

Inventor： JUNG KIM JUN ,  WIDODO JOHNNY ,  JAE-EUN PARK ,  SCHENK ANDRE ,  GUTMANN ALOIS ,  HAMPP ROLAND

Abstract: Dielectric layers are formed on a substrate by performing Subatmospheric Chemical Vapor Deposition (SACVD) of ozone-tetraethoxysilane (O 3 -TEOS) to form a layer of O 3 -TEOS on the substrate, and treating the layer of O 3 -TEOS with ultraviolet (UV) radiation. The UV radiation treatment can increase the tensile stress in the O 3 -TEOS layer by reducing the amount of water in the layer. Moreover, the UV treatment may also reduce the amount of silanol in the O 3 -TEOS layer, which can also increase reliability of the device.

公开(公告)号：DE102007018304A1

公开(公告)日：2007-10-31

申请号：DE102007018304

申请日：2007-04-18

Applicant: CHARTERED SEMICONDUCTOR MFG ,  INFINEON TECHNOLOGIES AG ,  SAMSUNG ELECTRONICS CO LTD

Inventor： GUTMANN ALOIS ,  HAMPP ROLAND ,  SCHENK ANDRE ,  KIM JUN JUNG ,  WIDODO JOHNNY ,  PARK JAE-EUN

IPC: H01L21/316 ,  H01L21/336 ,  H01L21/762

Abstract: Dielectric layers are formed on a substrate by performing Subatmospheric Chemical Vapor Deposition (SACVD) of ozone-tetraethoxysilane (O 3 -TEOS) to form a layer of O 3 -TEOS on the substrate, and treating the layer of O 3 -TEOS with ultraviolet (UV) radiation. The UV radiation treatment can increase the tensile stress in the O 3 -TEOS layer by reducing the amount of water in the layer. Moreover, the UV treatment may also reduce the amount of silanol in the O 3 -TEOS layer, which can also increase reliability of the device.

公开(公告)号：SG156622A1

公开(公告)日：2009-11-26

申请号：SG2009067166

申请日：2007-03-12

Applicant: CHARTERED SEMICONDUCTOR MFG ,  SAMSUNG ELECTRONICS CO LTD ,  INFINEON TECHNOLOGIES AG

Inventor： JUNG KIM JUN ,  WIDODO JOHNNY ,  JAE-EUN PARK ,  SCHENK ANDRE ,  GUTMANN ALOIS ,  HAMPP ROLAND

Abstract: ULTRAVIOLET (UV) RADIATION TREATMENT METHODS FOR SUBATMOSPHERIC CHEMICAL VAPOR DEPOSITION (SACVD) OF OZONE-TETRAETHOXYSILANE (03-TEOS) Dielectric layers are formed on a substrate by performing Subatmospheric Chemical Vapor Deposition (SACVD) of ozone-tetraethoxysilane (03-TEOS) to form a layer of 03-TEOS on the substrate, and treating the layer of 03-TEOS with ultraviolet (UV) radiation. The UV radiation treatment can increase the tensile stress in the 03-TEOS layer by reducing the amount of water in the layer. Moreover, the UV treatment may also reduce the amount of silanol in the 03-TEOS layer, which can also increase reliability of the device.

公开(公告)号：DE10241589A1

公开(公告)日：2004-03-25

申请号：DE10241589

申请日：2002-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  UHLENDORF INGO ,  SCHENK ANDRE ,  WOLLANKE ALEXANDER

IPC: H01L21/44 ,  H01L21/60 ,  H01L23/485

Abstract: Process for solder-stop structuring protrusions on wafers (3) such as three dimensional contact structures (1) in the form of elastic or flexible contact bumps comprises depositing a resist on the tip of the three dimensional structure, depositing a solder-stop layer over a metallization including the resist, and removing the resist on the tip of the three dimensional structure including the solder-stop layer covering it.