公开(公告)号：DE60116774T2

公开(公告)日：2006-08-31

申请号：DE60116774

申请日：2001-07-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHMANN GUNTHER ,  BRINTZINGER AXEL

IPC: H01L23/525

Abstract: A semiconductor device, in accordance with the present invention, includes a plurality of fuses disposed on a same level in a fuse bank. A plurality of conductive lines are routed through the fuse bank in between the fuses. A terminal via window is formed in a passivation layer over the plurality of conductive lines and over the plurality of fuses, the terminal via window being formed to expose the fuses in the fuse bank.

公开(公告)号：DE10158809B4

公开(公告)日：2006-08-31

申请号：DE10158809

申请日：2001-11-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL

IPC: H01L21/288 ,  H05K3/40 ,  H01L21/56 ,  H01L21/60 ,  H01L21/768

Abstract: Production of a conducting strip (4) on a passivated substrate (1) comprises: applying a mask to the substrate; structuring the mask to form an opening corresponding to the conducting strip; providing a conducting strip in the opening on the substrate; removing the mask; and encasing the conducting strip using a metal-selective wet chemical dip coating method. An Independent claim is also included for a corrosion-protected conductor strip produced by the above process. Preferred Features: A diffusion barrier and/or short circuit layer is applied to the substrate before applying the mask. The diffusion barrier and/or short circuit layer is made from a metal layer, preferably titanium. A support layer (3) is applied on the substrate before the mask is applied.

公开(公告)号：DE102004035080A1

公开(公告)日：2005-12-29

申请号：DE102004035080

申请日：2004-07-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TROVARELLI OCTAVIO ,  BRINTZINGER AXEL ,  UHLENDORF INGO ,  RUCKMICH STEFAN ,  WALLIS DAVID

IPC: H01L23/12 ,  H01L23/522 ,  H01L23/528

Abstract: An arrangement reduces the electrical crosstalk on a chip, in particular between adjacent conductors of the redistribution routing and/or between the redistribution routing on the first passivation on the chip and the metallization of the chip. In one aspect, the arrangement reduces the crosstalk between the redistribution wiring on a chip and its metallization and can be realized simply and independently at the front end. This is achieved by at least an additional conductor ( 10 ) being respectively arranged between adjacent conductors of the redistribution routing ( 1 ) and/or at least a second passivation ( 7 ) with a lower dielectric constant of a preferred "cold dielectric" being arranged between the redistribution routing ( 1 ) and the first passivation ( 2 ) on the active region of the chip ( 3 ).

公开(公告)号：DE102004005022A1

公开(公告)日：2005-08-25

申请号：DE102004005022

申请日：2004-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  TROVARELLI OCTAVIO ,  LEIBERG WOLFGANG

IPC: H01L21/768 ,  H01L23/532 ,  H05K3/10 ,  H05K3/24 ,  H01L51/10 ,  H05K1/09

Abstract: A method for fabricating a metallic conductor path with copper-nickel-gold layer structure, in which the copper core of the conductor path is electrically deposited on a copper seed layer (4) with a diffusion barrier arranged under it. Initially a dielectric mask (9) is formed so that the mask structure comprises the conductor path being fabricated, followed by extensive application of a copper-seed layer (4) carrying on the structure of the dielectric mask (9). A resist-mask is formed on the copper seed layer (4) by a first lithographic structuring of the positive resist, followed by galvanic deposition of the copper core (3) on the exposed copper seed layer (4). A second lithographic structuring of the resist mask follows, with subsequent application of nickel-gold-layer on the copper core (3) and removal of the resist mask and etching of the diffusion barrier (10) and the copper seed layer (4).

公开(公告)号：DE60011190D1

公开(公告)日：2004-07-08

申请号：DE60011190

申请日：2000-07-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH ,  KIRIHATA TOSHIAKI ,  DANIEL GABRIEL ,  LACHTRUPP DAVID ,  BRINTZINGER AXEL

IPC: H01L21/82 ,  H01H85/00 ,  H01H85/02 ,  H01H85/044 ,  H01H85/046 ,  H01L21/66 ,  H01L23/525 ,  H01L27/02

Abstract: A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.

公开(公告)号：DE10258094A1

公开(公告)日：2004-07-08

申请号：DE10258094

申请日：2002-12-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  UHLENDORF INGO

IPC: H01L21/60 ,  H01L23/485

Abstract: An electrophoretic resist (ER) (5) is used as a photoresist. A wafer (1) is coated with the ER by dipping the wafer's active side in the ER and by applying an electric voltage between the wafer and the ER. The rear side of the wafer is protected from wetting during dipping of the active side in the ER. The coating is baked.

公开(公告)号：DE10258081A1

公开(公告)日：2004-07-08

申请号：DE10258081

申请日：2002-12-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL

IPC: H01L21/60 ,  H01L23/485

Abstract: Production of a solder stop arrangement comprises depositing a seed layer on a wafer (2) and carrying out a lithography step with a resist to structure a reroute layer of each bond pad for a three-dimensional structure (1), and reroute plating by depositing a nickel/copper layer on the seed layer. The wafer is provided with a low viscosity coating made from an organic material which leaves open the tip of the three-dimensional structure and a gold layer (5) is deposited on the tip.

公开(公告)号：DE10158809A1

公开(公告)日：2003-06-18

申请号：DE10158809

申请日：2001-11-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL

IPC: H05K3/40 ,  H01L21/288 ,  H01L21/60 ,  H01L21/768 ,  H01L21/56

Abstract: Production of a conducting strip (4) on a passivated substrate (1) comprises: applying a mask to the substrate; structuring the mask to form an opening corresponding to the conducting strip; providing a conducting strip in the opening on the substrate; removing the mask; and encasing the conducting strip using a metal-selective wet chemical dip coating method. An Independent claim is also included for a corrosion-protected conductor strip produced by the above process. Preferred Features: A diffusion barrier and/or short circuit layer is applied to the substrate before applying the mask. The diffusion barrier and/or short circuit layer is made from a metal layer, preferably titanium. A support layer (3) is applied on the substrate before the mask is applied.

公开(公告)号：DE10240401A1

公开(公告)日：2003-04-03

申请号：DE10240401

申请日：2002-09-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL

IPC: G01R1/04 ,  G01R3/00 ,  B81C1/00 ,  H01L21/68

Abstract: A method for fabricating a structure on an integrated circuit wafer, includes applying an anti-sticking coating to a surface of a mold, depositing a first material on the anti-sticking coating, and removing a portion of the first material to expose the anti-sticking coating. A first interface between the mold and the first material has a first adhesiveness. The process also includes placing the anti-sticking coating in contact with the wafer, and removing the mold from the wafer. A second interface between the first material and the wafer has a second adhesiveness that is greater than the first adhesiveness.

公开(公告)号：DE60126960D1

公开(公告)日：2007-04-12

申请号：DE60126960

申请日：2001-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL

IPC: H01L23/00 ,  H01L23/58

Abstract: A semiconductor chip, in accordance with the present invention, includes a substrate and a crack stop structure. The crack structure includes a first conductive line disposed over the substrate and at least two first contacts connected to the substrate and to the first conductive line. The at least two first contacts are spaced apart from each other and extend longitudinally along a length of the first conductive line. A second conductive line is disposed over a portion of the first conductive line, and at least two second contacts are connected to the first conductive line and the second conductive line. The at least two second contacts are spaced apart from each other and extend longitudinally along a length of the second conductive line.