公开(公告)号：DE10341564B4

公开(公告)日：2007-11-22

申请号：DE10341564

申请日：2003-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHRENK MICHAEL ANTON

IPC: H01L27/08 ,  H01G4/005 ,  H01L21/02 ,  H01L21/822

Abstract: On substrate (120) is deposited first conductive auxiliary layer (122). Capacitor dielectric (124) is coupled to first auxiliary layer within first boundary surface (128) between dielectric and first auxiliary layer.Second conductive layer (126) is coupled to dielectric within second boundary surface (130) between dielectric and second auxiliary layer. Effective capacitor region (140) is provided at overlapping of both boundary surfaces over dielectric. Application of contact electrode (132) in contact region (134) is specified. INDEPENDENT CLAIM is included for forming capacitor unit.

公开(公告)号：DE10161286A1

公开(公告)日：2003-07-03

申请号：DE10161286

申请日：2001-12-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHRENK MICHAEL ANTON ,  KOLLER KLAUS ,  KOERNER HEINRICH

IPC: H01L21/02 ,  H01L21/768 ,  H01L27/08 ,  H01L29/92

Abstract: To produce an integrated semiconductor product comprising an integrated metal-insulator-metal capacitor, a dielectric auxiliary layer (6) is first deposited on a first electrode (2, 3, 5). Said auxiliary layer (6) is then opened over the first electrode (15). A dielectric layer (7) is then created, onto which the stack (8, 9, 10) of metal strips for the second electrode is applied. The metal-insulator-metal capacitor is subsequently patterned using conventional etching technology. This allows the production of dielectric capacitor layers comprising freely selectable materials of any thickness. The particular advantage of the invention is that the etching of vias can be carried out in a significantly simpler manner than in prior art, as it is not necessary to etch through the remaining dielectric capacitor layer over the metal strips.

公开(公告)号：DE10341564A1

公开(公告)日：2005-04-07

申请号：DE10341564

申请日：2003-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHRENK MICHAEL ANTON

IPC: H01L21/02 ,  H01L27/08 ,  H01L21/822

Abstract: On substrate (120) is deposited first conductive auxiliary layer (122). Capacitor dielectric (124) is coupled to first auxiliary layer within first boundary surface (128) between dielectric and first auxiliary layer.Second conductive layer (126) is coupled to dielectric within second boundary surface (130) between dielectric and second auxiliary layer. Effective capacitor region (140) is provided at overlapping of both boundary surfaces over dielectric. Application of contact electrode (132) in contact region (134) is specified. INDEPENDENT CLAIM is included for forming capacitor unit.

公开(公告)号：DE10161285A1

公开(公告)日：2003-07-03

申请号：DE10161285

申请日：2001-12-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHRENK MICHAEL ANTON ,  SCHWERD MARKUS ,  KOERNER HEINRICH

IPC: H01L21/02 ,  H01L21/768 ,  H01L27/08 ,  H01L29/92

Abstract: According to the invention, in order to produce an integrated semiconductor product comprising integrated metal-insulator-metal capacitors, a dielectric protective layer (5) and a dielectric auxiliary layer (16) are first deposited on a first electrode (2). Said protective layer and said auxiliary layer (16) are then removed (17) from the region above the first electrode, and a dielectric layer (6) is produced, the pile of metallic strips (7, 8, 9) for the second electrode being applied to said dielectric layer. The metal-insulator-metal capacitor is then structured according to known etching methods. Dielectric capacitor layers consisting of freely selectable materials and having any thickness can be formed in this way. The present invention is especially advantageous in that it enables via holes to be etched in a significantly more simple manner than according to prior art, as the remaining dielectric capacitor layer covering the metallic strips does not need to be etched through.