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    4.
    发明专利
    未知

    公开(公告)号：DE10341059A1

    公开(公告)日：2005-04-14

    申请号：DE10341059

    申请日：2003-09-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HELNEDER JOHANN ,  SCHWERD MARKUS ,  GOEBEL THOMAS ,  MITCHELL ANDREA ,  KOERNER HEINRICH ,  SECK MARTIN ,  TORWESTEN HOLGER

    IPC: H01L21/02 ,  H01L21/316 ,  H01L23/522 ,  H01L27/01 ,  H01L27/08 ,  H01L21/822 ,  H01G9/042

    Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.

    Verfahren zum Vereinzeln von einer Vielzahl von Chips
    5.
    发明专利
    Verfahren zum Vereinzeln von einer Vielzahl von Chips 未知

    公开(公告)号：DE102015120756A1

    公开(公告)日：2017-06-01

    申请号：DE102015120756

    申请日：2015-11-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PÜSCHNER FRANK ,  SCHWERD MARKUS ,  SAVIGNAC DOMINIQUE

    IPC: H01L21/301 ,  H01L21/304 ,  H01L21/78

    Abstract: Ein Chip kann ein Substrat (104), einen in und/oder auf dem Substrat (104) angeordneten aktiven Bereich (106), in dem mindestens eine elektronische Komponente gebildet ist und ein Dielektrikum (108) über dem aktiven Bereich (106) aufweisen. Ein Verfahren zum Vereinzeln von einer Vielzahl von Chips (112) kann das Bilden von mindestens einem Vereinzelungsbereich (120) zwischen der Vielzahl von Chips (112) aufweisen, wobei jeder Vereinzelungsbereich (120) einen Randbereich (122) und einen Zentralbereich (124) aufweist, wobei in mindestens einem Zentralbereich (124) eine Metallstruktur (114) angeordnet ist. Ferner kann das Verfahren zum Vereinzeln von einer Vielzahl von Chips (114) das Bilden von mindestens einer Grabenstruktur (126) in dem Randbereich (122) zwischen der Vielzahl von Chips (112) aufweisen, wobei eine jeweilige Grabenstruktur (126) einen jeweiligen Zentralbereich (124) umgibt, und wobei die mindestens eine Grabenstruktur (126) zumindest durch das Dielektrikum (108) hindurch gebildet wird. Weiterhin kann das Verfahren ein nachfolgendes Vereinzeln der Vielzahl von Chips (112) entlang des mindestens einen Vereinzelungsbereichs (120) aufweisen.

    Production of a through-contact used in the production of integrated circuits comprises forming an insulating layer, forming a contact opening in a contact region, and filling the contact opening with a conducting material
    8.
    发明专利
    Production of a through-contact used in the production of integrated circuits comprises forming an insulating layer, forming a contact opening in a contact region, and filling the contact opening with a conducting material 未知

    公开(公告)号：DE10201448A1

    公开(公告)日：2003-07-24

    申请号：DE10201448

    申请日：2002-01-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KLEIN WOLFGANG ,  SCHWERD MARKUS ,  KOLLER KLAUS

    IPC: H01L21/768 ,  H01L23/522 ,  H01L21/283

    Abstract: Production of a through-contact (34) comprises forming an insulating layer (56), forming a contact opening (76) in a contact region extending from the second main side (59) of the insulating layer up to a first strip conductor (18) and opening into a trench, and filling the contact opening with a conducting material (78) to produce the through-contact and a second strip conductor (10) so that the width of the second strip conductor can be fitted in a self-adjusting manner to the size of the through-contact. An Independent claim is also included for the through-contact formed by the above process. Preferred Features: The step of filling the contact opening comprises also filling the trench for the second strip conductor with the conducting material to produce the second strip conductor. The insulating layer is produced by forming a further insulating layer, forming a trench for the first strip conductor in a main side of the further insulating layer, filling the trench with a conducting material to form the first strip conductor, applying the insulating layer on the main side of the further insulating layer, and forming the trench for the second strip conductor in the main side of the insulating layer lying opposite the further insulating layer.

    9.
    发明专利
    未知

    公开(公告)号：DE10161285A1

    公开(公告)日：2003-07-03

    申请号：DE10161285

    申请日：2001-12-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHRENK MICHAEL ANTON ,  SCHWERD MARKUS ,  KOERNER HEINRICH

    IPC: H01L21/02 ,  H01L21/768 ,  H01L27/08 ,  H01L29/92

    Abstract: According to the invention, in order to produce an integrated semiconductor product comprising integrated metal-insulator-metal capacitors, a dielectric protective layer (5) and a dielectric auxiliary layer (16) are first deposited on a first electrode (2). Said protective layer and said auxiliary layer (16) are then removed (17) from the region above the first electrode, and a dielectric layer (6) is produced, the pile of metallic strips (7, 8, 9) for the second electrode being applied to said dielectric layer. The metal-insulator-metal capacitor is then structured according to known etching methods. Dielectric capacitor layers consisting of freely selectable materials and having any thickness can be formed in this way. The present invention is especially advantageous in that it enables via holes to be etched in a significantly more simple manner than according to prior art, as the remaining dielectric capacitor layer covering the metallic strips does not need to be etched through.

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