公开(公告)号：WO2005045931A3

公开(公告)日：2005-08-11

申请号：PCT/DE2004002440

申请日：2004-11-03

Applicant: INFINEON TECHNOLOGIES AG ,  OFNER GERALD ,  TEO MARY ,  TAN AI MIN

Inventor： OFNER GERALD ,  TEO MARY ,  TAN AI MIN

IPC: H01L21/56 ,  H01L23/485 ,  H01L23/498

CPC classification number: H01L24/10 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01014 ,  H01L2924/01052 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

Abstract: The invention relates to a semiconductor chip (1) having flip-chip contacts (2), whereby the flip-chip contacts (2) are placed on contact surfaces (3) of the active top side (4) of the semiconductor chip (1). The contact surfaces (3) are surrounded by a passivation layer (5) that covers the active top side (4) while leaving the contact surfaces (3) exposed. The passivation layer (5) comprises thickenings (6) that encircle the contact surfaces (3). A semiconductor layer (1) of this type with thickenings (6) encircling the contact surfaces (3) is protected from delamination when packing the semiconductor chip (1) to form a semiconductor component.

Abstract translation: 本发明涉及一种半导体芯片（1）与倒装片触点（2），其中，所述倒装芯片触点（2）接触的区域（3）的有源顶部侧（4）的半导体芯片（1）的布置。 的接触表面（3）是含有活性顶侧（4）覆盖，而留下的接触区域所包围的钝化层（5）的（3）。 钝化层（5）具有加厚部分（6），其围绕所述接触区域（3）。 这样的半导体芯片（1）具有加厚部分（6）周围的接触面（3）在剥离前的半导体芯片（1）的包装被保护的半导体器件。

公开(公告)号：DE10352349A1

公开(公告)日：2005-06-23

申请号：DE10352349

申请日：2003-11-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OFNER GERALD ,  TAN AI MIN ,  TEO MARY

IPC: H01L21/56 ,  H01L23/485 ,  H01L23/498 ,  H01L23/50 ,  H01L23/28 ,  H01L21/50

Abstract: A semiconductor chip includes flip chip contacts that are arranged on contact surfaces of an active top side of the semiconductor chip. The contact surfaces are surrounded by a passivation layer that covers the active top side while leaving exposed the contact surfaces. The passivation layer includes thickened portions that surround the contact surfaces. The semiconductor chip formed with thickened portions around the contact surfaces is protected from delamination during packaging of the semiconductor chip to form a semiconductor device.

公开(公告)号：DE10352349B4

公开(公告)日：2006-11-16

申请号：DE10352349

申请日：2003-11-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OFNER GERALD ,  TAN AI MIN ,  TEO MARY

IPC: H01L23/50 ,  H01L21/50 ,  H01L21/56 ,  H01L23/28 ,  H01L23/485 ,  H01L23/498

Abstract: A semiconductor chip includes flip chip contacts that are arranged on contact surfaces of an active top side of the semiconductor chip. The contact surfaces are surrounded by a passivation layer that covers the active top side while leaving exposed the contact surfaces. The passivation layer includes thickened portions that surround the contact surfaces. The semiconductor chip formed with thickened portions around the contact surfaces is protected from delamination during packaging of the semiconductor chip to form a semiconductor device.

公开(公告)号：DE112005003634T5

公开(公告)日：2008-06-12

申请号：DE112005003634

申请日：2005-08-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OFNER GERALD ,  YEO SWAIN HONG ,  TEO MARY ,  LIM PEI SIANG ,  CHUA KHOON LAM

IPC: H01L21/56

Abstract: A method of forming an integrated circuit package, such as a Flip Chip package, in which a void is provided in the underfill material in the central region of the package between the chip or die and the substrate on which the chip or die is mounted. This reduces delamination of the package as a result of moisture.