公开(公告)号：DE69835180T2

公开(公告)日：2007-06-14

申请号：DE69835180

申请日：1998-03-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TOBBEN DIRK ,  WEIGAND PETER

IPC: H01L27/04 ,  H01L27/108 ,  B81B3/00 ,  H01L21/02 ,  H01L21/32 ,  H01L21/822 ,  H01L21/8242

Abstract: A method for forming a microstructure includes photolithographically forming a vertically extending post on a portion of a surface of a substrate to provide a first structure. A flowable, sacrificial material is deposited over a surface of the first structure. The flowable, sacrificial materially flows off the top surface and sidewall portions of the post onto adjacent portions of the surface of the substrate to provide a second structure. A non-sacrificial material is deposited over a surface of the second structure. The non-sacrificial material is deposited to conform to the surface of the second structure. The non-sacrificial is deposited over the sacrificial material, over the sidewall portions and over the top surface of the post. The deposited sacrificial material is selectively removed while the non-sacrificial material remains to form a third structure with a horizontal member provided by the non-sacrificial material. The horizontal member is supported a predetermined distance above the surface of the substrate by a lower portion of the post. The flowable material is a flowable oxide, for example, hydrogensilsesquioxane glass, and the post has a width less than 20 mu m. The resulting structure, formed with a single photolithographic step, is used for supporting a capacitor deposited over it. The capacitor is formed as a sequence of deposition steps; i.e., depositing a first conductive layer over a surface of the support structure; depositing a dielectric layer over the conductive layer; and depositing a second conductive layer over the dielectric layer.

公开(公告)号：DE69834686T2

公开(公告)日：2007-05-31

申请号：DE69834686

申请日：1998-03-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TOBBEN DIRK ,  SPULER BRUNO ,  GUTSCHE MARTIN ,  WEIGAND PETER

IPC: H01L21/768 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L23/12 ,  H05K1/00 ,  H05K3/06 ,  H05K3/22 ,  H05K3/24

Abstract: A method for forming a plurality of electrically conductive wires on a substrate. The method includes forming a relatively non-planar metal layer over a surface of the substrate. A self-planarizing material is deposited over the metal layer. The self-planarizing material forms a planarization layer over the surface of the metal layer. The planarization layer has a surface relatively planar compared to the relatively non-planar metal layer. A photoresist layer is deposited over the surface of the planarization layer. The photoresist layer is patterned with a plurality of grooves to form a mask with such grooves exposing underling portions of the planarization layer. The photoresist mask is used as a mask to etch grooves in the exposed portions of the planarization layer and thereby form a second mask. The second mask exposes underling portions of the relatively non-planar metal layer. The second mask is used to etch grooves in the relatively non-planar conductive metal layer and thereby form the plurality of electrically conductive wires in the metal layer. The wires are separated from each other by the grooves formed in the relatively non-planar metal layer. The planarization layer is formed by a spinning-on an organic polymer, for example an organic polymer having silicon, or a flowable oxide, or a hydrogensilsequioxane, or divinyl-siloxane-benzocyclobutene. The metal layer is etched using reactive ion etching. The planarization layer is removed using a wet chemical etch.

公开(公告)号：DE69835180D1

公开(公告)日：2006-08-24

申请号：DE69835180

申请日：1998-03-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TOBBEN DIRK ,  WEIGAND PETER

IPC: H01L27/04 ,  H01L27/108 ,  B81B3/00 ,  H01L21/02 ,  H01L21/32 ,  H01L21/822 ,  H01L21/8242

Abstract: A method for forming a microstructure includes photolithographically forming a vertically extending post on a portion of a surface of a substrate to provide a first structure. A flowable, sacrificial material is deposited over a surface of the first structure. The flowable, sacrificial materially flows off the top surface and sidewall portions of the post onto adjacent portions of the surface of the substrate to provide a second structure. A non-sacrificial material is deposited over a surface of the second structure. The non-sacrificial material is deposited to conform to the surface of the second structure. The non-sacrificial is deposited over the sacrificial material, over the sidewall portions and over the top surface of the post. The deposited sacrificial material is selectively removed while the non-sacrificial material remains to form a third structure with a horizontal member provided by the non-sacrificial material. The horizontal member is supported a predetermined distance above the surface of the substrate by a lower portion of the post. The flowable material is a flowable oxide, for example, hydrogensilsesquioxane glass, and the post has a width less than 20 mu m. The resulting structure, formed with a single photolithographic step, is used for supporting a capacitor deposited over it. The capacitor is formed as a sequence of deposition steps; i.e., depositing a first conductive layer over a surface of the support structure; depositing a dielectric layer over the conductive layer; and depositing a second conductive layer over the dielectric layer.

公开(公告)号：DE69737433D1

公开(公告)日：2007-04-19

申请号：DE69737433

申请日：1997-08-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEIGAND PETER

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/3105

Abstract: Described is a method for filling shallow trench isolation (STI) trenches in a semiconductor substrate of an integrated circuit with an insulating material and planarizing the resulting structure to the level of adjacent portions of the integrated circuit. The method comprises forming trenches in the non-active regions of a semiconductor substrate, depositing a layer of oxide in the trenches and over the surface of the semiconductor substrate, and removing the oxide from the active areas of the integrated circuit structure, leaving oxide-filled shallow trench isolation structures having a substantially planar topography with respect to the rest of the integrated circuit structure.

公开(公告)号：DE69834988D1

公开(公告)日：2006-08-03

申请号：DE69834988

申请日：1998-09-04

Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KAWASAKI KK

Inventor： WEIGAND PETER ,  SHODA BAIGURI

IPC: G01K13/02 ,  H01L21/00 ,  H01J37/00 ,  H01J37/32 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/66

Abstract: Apparatus and method are provided for obtaining improved measurement and control of the temperature of a semiconductor wafer (W) during processing. The apparatus includes a chuck for holding a wafer during processing, a coolant gas supply (16), and a temperature sensing arrangement for measuring and controlling the temperature of the wafer during processing. A top face of the chuck (22) over which the wafer is positioned, is configured with a plurality of holes (34) into which the coolant gas, such as helium, is admitted at controlled rate and pressure. The coolant gas passes through a narrow space (36) between the top face of the chuck and the underside of the wafer and is evacuated via an exhaust line (30) after being heated to (or nearly to) the temperature of the wafer. Temperature of the now-heated coolant gas is continuously measured by a temperature sensor arrangement which generates a signal controlling the pressure and flow of coolant gas to the wafer. Close control of the temperature of the wafer is thereby maintained continuously at a desired value during processing.

公开(公告)号：DE69834686D1

公开(公告)日：2006-07-06

申请号：DE69834686

申请日：1998-03-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TOBBEN DIRK ,  SPULER BRUNO ,  GUTSCHE MARTIN ,  WEIGAND PETER

IPC: H01L21/768 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L23/12 ,  H05K1/00 ,  H05K3/06 ,  H05K3/22 ,  H05K3/24

Abstract: A method for forming a plurality of electrically conductive wires on a substrate. The method includes forming a relatively non-planar metal layer over a surface of the substrate. A self-planarizing material is deposited over the metal layer. The self-planarizing material forms a planarization layer over the surface of the metal layer. The planarization layer has a surface relatively planar compared to the relatively non-planar metal layer. A photoresist layer is deposited over the surface of the planarization layer. The photoresist layer is patterned with a plurality of grooves to form a mask with such grooves exposing underling portions of the planarization layer. The photoresist mask is used as a mask to etch grooves in the exposed portions of the planarization layer and thereby form a second mask. The second mask exposes underling portions of the relatively non-planar metal layer. The second mask is used to etch grooves in the relatively non-planar conductive metal layer and thereby form the plurality of electrically conductive wires in the metal layer. The wires are separated from each other by the grooves formed in the relatively non-planar metal layer. The planarization layer is formed by a spinning-on an organic polymer, for example an organic polymer having silicon, or a flowable oxide, or a hydrogensilsequioxane, or divinyl-siloxane-benzocyclobutene. The metal layer is etched using reactive ion etching. The planarization layer is removed using a wet chemical etch.

公开(公告)号：DE69834988T2

公开(公告)日：2007-02-08

申请号：DE69834988

申请日：1998-09-04

Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KAWASAKI KK

Inventor： WEIGAND PETER ,  SHODA BAIGURI

IPC: G01K13/02 ,  H01L21/00 ,  H01J37/00 ,  H01J37/32 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/66

Abstract: Apparatus and method are provided for obtaining improved measurement and control of the temperature of a semiconductor wafer (W) during processing. The apparatus includes a chuck for holding a wafer during processing, a coolant gas supply (16), and a temperature sensing arrangement for measuring and controlling the temperature of the wafer during processing. A top face of the chuck (22) over which the wafer is positioned, is configured with a plurality of holes (34) into which the coolant gas, such as helium, is admitted at controlled rate and pressure. The coolant gas passes through a narrow space (36) between the top face of the chuck and the underside of the wafer and is evacuated via an exhaust line (30) after being heated to (or nearly to) the temperature of the wafer. Temperature of the now-heated coolant gas is continuously measured by a temperature sensor arrangement which generates a signal controlling the pressure and flow of coolant gas to the wafer. Close control of the temperature of the wafer is thereby maintained continuously at a desired value during processing.