公开(公告)号：WO02086903A3

公开(公告)日：2003-10-09

申请号：PCT/DE0201504

申请日：2002-04-24

Applicant: INFINEON TECHNOLOGIES AG ,  OBERGRUSSBERGER FRANZ-XAVER ,  BAENISCH ANDREAS ,  ZIMMERMANN ELLEN

Inventor： OBERGRUSSBERGER FRANZ-XAVER ,  BAENISCH ANDREAS ,  ZIMMERMANN ELLEN

IPC: G11C7/16 ,  G11C5/06 ,  G11C8/10 ,  G11C27/00

CPC classification number: G11C7/16

Abstract: According to the invention, a plurality of digital-analogue converters (60, 61) and analogue-digital converters are positioned in the data lines (20, 21) between the connection contacts (3) and the memory cells (1), in such a way that the reading, writing and control of the memory takes place by analogue data transfers instead of the previous digital signatures. It is therefore possible to read, by means of a single connection contact, the same quantity of data, which would usually necessitate several connection contact surfaces (pads). Respective contact surfaces for the analogue line address and the analogue column address are sufficient for addressing the memory cells, said addresses being converted into digital addresses using analogue-digital converters.

Abstract translation: 多个数字到模拟的连接触点（3）和所述存储单元之间的转换器（60，61）和模拟 - 数字转换器在所述数据线（20，21）（1）存在时，使得读，写和 驱动存储器可以由模拟数据传送，而不是前面的数字信号来完成。 需要为常多个端子的接触面（垫）的数据相同量的，因此可以仅由一个端子接触被读出。 分别满足接触表面用于模拟行地址和列地址的模拟，其与模拟 - 数字转换器，用于寻址所述存储器单元反应成数字地址。

公开(公告)号：DE10120054A1

公开(公告)日：2002-11-07

申请号：DE10120054

申请日：2001-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAENISCH ANDREAS ,  ZIMMERMANN ELLEN ,  OBERGRUSSBERGER XAVER

IPC: G11C7/16 ,  G11C7/00

Abstract: According to the invention, a plurality of digital-analogue converters (60, 61) and analogue-digital converters are positioned in the data lines (20, 21) between the connection contacts (3) and the memory cells (1), in such a way that the reading, writing and control of the memory takes place by analogue data transfers instead of the previous digital signatures. It is therefore possible to read, by means of a single connection contact, the same quantity of data, which would usually necessitate several connection contact surfaces (pads). Respective contact surfaces for the analogue line address and the analogue column address are sufficient for addressing the memory cells, said addresses being converted into digital addresses using analogue-digital converters.

公开(公告)号：DE10130978A1

公开(公告)日：2003-01-16

申请号：DE10130978

申请日：2001-06-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  ZIMMERMANN ELLEN

IPC: G11C29/00

Abstract: A RAM circuit has a memory cell array whose number of rows is an integer multiple of an integer p>1 and is composed of regular and redundant rows. Each row is assigned a driver. The space occupied by the cell array and by the drivers is subdivided into two sections, in each of which there is situated a subset of the regular rows and a subset of the redundant rows. In the first section, the number of rows is by a number k smaller than an integer multiple of p. In each section, each driver occupies a location allocated to it in a regular two-dimensional pattern of locations, each of which has one of p possible X coordinates in the row direction. The locations of the pattern are occupied without any vacancies within the first section, and, within the second section, p-k locations of the pattern are unoccupied.

公开(公告)号：DE10120054B4

公开(公告)日：2008-01-03

申请号：DE10120054

申请日：2001-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAENISCH ANDREAS ,  ZIMMERMANN ELLEN ,  OBERGRUSSBERGER XAVER

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/16

Abstract: A plurality of digital-analog converters and analog-digital converters are connected in the data lines between the connection contacts and the memory cells of a memory device. The memory can be read, written to and actuated by analog data transfers instead of the previous digital signals. The same volume of data, for which a plurality of connection contact areas were normally required, can thus be read via just one connection contact. Addressing the memory cells requires no more than respective contact areas for the analog row address and the analog column address, which are converted into digital addresses using analog-digital converters.

公开(公告)号：DE10130978C2

公开(公告)日：2003-09-25

申请号：DE10130978

申请日：2001-06-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  ZIMMERMANN ELLEN

IPC: G11C29/00

Abstract: A RAM circuit has a memory cell array whose number of rows is an integer multiple of an integer p>1 and is composed of regular and redundant rows. Each row is assigned a driver. The space occupied by the cell array and by the drivers is subdivided into two sections, in each of which there is situated a subset of the regular rows and a subset of the redundant rows. In the first section, the number of rows is by a number k smaller than an integer multiple of p. In each section, each driver occupies a location allocated to it in a regular two-dimensional pattern of locations, each of which has one of p possible X coordinates in the row direction. The locations of the pattern are occupied without any vacancies within the first section, and, within the second section, p-k locations of the pattern are unoccupied.