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    INTEGRATED SEMICONDUCTOR CHIP
    1.
    发明专利
    INTEGRATED SEMICONDUCTOR CHIP 失效

    公开(公告)号：JP2001077203A

    公开(公告)日：2001-03-23

    申请号：JP2000237577

    申请日：2000-08-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BAENISCH ANDREAS ,  KLING SABINE

    IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/82 ,  H01L23/522 ,  H01L23/528

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor chip, comprising at least two metal lines, of two different metalized surfaces, extending orthogonally each other, reducing the required space for minimize the election movement effect for mutual contact connection. SOLUTION: In this semiconductor chip, at least one metal line 1 of a first metalized surface and a metal line 2 of a second metalized surface are provided. The metalized surfaces are parallel to each other, while at least one conductive contact point 3 is provided between the metal lines. The metal lines are orthogonal to each other in a first region, where they are not contact-connected via the contact point, while being parallel to each other and being diagonal with respect to the direction of metal line in the first region, in a second region 20, where they are contact-connected via the contact point.

    SEMICONDUCTOR MEMORY ELEMENT
    2.
    发明申请
    SEMICONDUCTOR MEMORY ELEMENT 审中-公开
    半导体存储元件

    公开(公告)号：WO02086903A3

    公开(公告)日：2003-10-09

    申请号：PCT/DE0201504

    申请日：2002-04-24

    Applicant: INFINEON TECHNOLOGIES AG ,  OBERGRUSSBERGER FRANZ-XAVER ,  BAENISCH ANDREAS ,  ZIMMERMANN ELLEN

    Inventor： OBERGRUSSBERGER FRANZ-XAVER ,  BAENISCH ANDREAS ,  ZIMMERMANN ELLEN

    IPC: G11C7/16 ,  G11C5/06 ,  G11C8/10 ,  G11C27/00

    CPC classification number: G11C7/16

    Abstract: According to the invention, a plurality of digital-analogue converters (60, 61) and analogue-digital converters are positioned in the data lines (20, 21) between the connection contacts (3) and the memory cells (1), in such a way that the reading, writing and control of the memory takes place by analogue data transfers instead of the previous digital signatures. It is therefore possible to read, by means of a single connection contact, the same quantity of data, which would usually necessitate several connection contact surfaces (pads). Respective contact surfaces for the analogue line address and the analogue column address are sufficient for addressing the memory cells, said addresses being converted into digital addresses using analogue-digital converters.

    Abstract translation: 多个数字到模拟的连接触点（3）和所述存储单元之间的转换器（60，61）和模拟 - 数字转换器在所述数据线（20，21）（1）存在时，使得读，写和 驱动存储器可以由模拟数据传送，而不是前面的数字信号来完成。 需要为常多个端子的接触面（垫）的数据相同量的，因此可以仅由一个端子接触被读出。 分别满足接触表面用于模拟行地址和列地址的模拟，其与模拟 - 数字转换器，用于寻址所述存储器单元反应成数字地址。

    3.
    发明专利
    未知

    公开(公告)号：DE10120054B4

    公开(公告)日：2008-01-03

    申请号：DE10120054

    申请日：2001-04-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BAENISCH ANDREAS ,  ZIMMERMANN ELLEN ,  OBERGRUSSBERGER XAVER

    IPC: G11C7/00 ,  G11C7/10 ,  G11C7/16

    Abstract: A plurality of digital-analog converters and analog-digital converters are connected in the data lines between the connection contacts and the memory cells of a memory device. The memory can be read, written to and actuated by analog data transfers instead of the previous digital signals. The same volume of data, for which a plurality of connection contact areas were normally required, can thus be read via just one connection contact. Addressing the memory cells requires no more than respective contact areas for the analog row address and the analog column address, which are converted into digital addresses using analog-digital converters.

    7.
    发明专利
    未知

    公开(公告)号：DE10045045C2

    公开(公告)日：2002-09-19

    申请号：DE10045045

    申请日：2000-09-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ANGERMANN WOLFGANG ,  BAENISCH ANDREAS

    IPC: H01L29/41 ,  H01L21/335 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L21/336

    Abstract: Production of MOS transistors in integrated semiconductor circuits. Production method comprises: (i) etching a substrate section from a main surface of the substrate between source and drain regions (S, D) assigned to a field effect transistor; (ii) forming a first gate region (G1) in the etched substrate section so that the first gate region lies between the source and drain region; (iii) filling the etched substrate section above the gate region with semiconductor material (Si); (iv) creating a second gate region (G2) above the first gate region sandwiching the semiconductor material; and (v) connecting the gate regions on one side with electrically conducting material. Preferred Features: One substrate section containing the field effect transistor is a p-doped silicon substrate section and the drain and source regions contain n-silicon and the gate region contains SiO2.

    8.
    发明专利
    未知

    公开(公告)号：DE10045045A1

    公开(公告)日：2002-04-04

    申请号：DE10045045

    申请日：2000-09-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ANGERMANN WOLFGANG ,  BAENISCH ANDREAS

    IPC: H01L29/41 ,  H01L21/335 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L21/336

    Abstract: Production of MOS transistors in integrated semiconductor circuits. Production method comprises: (i) etching a substrate section from a main surface of the substrate between source and drain regions (S, D) assigned to a field effect transistor; (ii) forming a first gate region (G1) in the etched substrate section so that the first gate region lies between the source and drain region; (iii) filling the etched substrate section above the gate region with semiconductor material (Si); (iv) creating a second gate region (G2) above the first gate region sandwiching the semiconductor material; and (v) connecting the gate regions on one side with electrically conducting material. Preferred Features: One substrate section containing the field effect transistor is a p-doped silicon substrate section and the drain and source regions contain n-silicon and the gate region contains SiO2.

    9.
    发明专利
    未知

    公开(公告)号：DE102004062885B4

    公开(公告)日：2007-10-18

    申请号：DE102004062885

    申请日：2004-12-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHAMBERGER FLORIAN ,  SOMMER MICHAEL BERNHARD ,  BAENISCH ANDREAS

    IPC: H01R12/04 ,  H01L23/50 ,  H01R13/20 ,  H05K1/18

    Abstract: Fastener (1) has a carrier element (2) and multitude of fastening elements (3). The fastening elements are arranged on the carrier element and comprises in each case an oblong body, which protrudes from carrier element and possesses a suitable form between further fastening elements for engaging and/or hooking. Fastening elements and carrier element are electrically conductive on their surface. Independent claims are also included for the following: (A) Electronic component; (B) Arrangement with an electronic conductor board and a semiconductor unit; and (C) Procedure for fastening semiconductor unit on an electronic conductor board.

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