公开(公告)号：JP2000331474A

公开(公告)日：2000-11-30

申请号：JP2000130113

申请日：2000-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZORUTAN MANYOOKI ,  ROEHR THOMAS ,  BOEHM THOMAS

IPC: G11C14/00 ,  G11C7/06 ,  G11C7/10 ,  G11C11/22

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption under an area required for column selection line path by connecting each bit line to a sense amplifier to which a bit line belongs through a first switching element, and connecting each bit line to a standby potential through a second switching element. SOLUTION: All column selection lines LCSLK takes a low potential so far as any column is not selected out of plural columns. Consequently, a first transistor A is made non-conduction state, and a second transistor B is conducted. Therefore, bit lines BL , bBL at the edge of cellfield AR are decoupled to a sense amplifier SA, and are in a standby potential VSTB. Consequently, a selection transistor T of a memory cell MC is made a non- conduction state. Thereby, contents of a memory of the memory cell MC is not affected at the time of access.