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    INTEGRATED MEMORY, AND METHOD FOR GENERATING REFERENCE VOLTAGE ON REFERENCE BIT LINE OF INTEGRATED MEMORY
    2.
    发明专利
    INTEGRATED MEMORY, AND METHOD FOR GENERATING REFERENCE VOLTAGE ON REFERENCE BIT LINE OF INTEGRATED MEMORY 失效

    公开(公告)号：JP2001307478A

    公开(公告)日：2001-11-02

    申请号：JP2001083633

    申请日：2001-03-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  MANYOKI ZOLTAN ,  ESTERL ROBERT ,  ROEHR THOMAS

    IPC: G11C11/22

    Abstract: PROBLEM TO BE SOLVED: To improve accuracy of bit line reference voltage to read and write data in a memory capacitor MC in a memory in which a differential sense amplifier SA is connected to a pair of bit lines, for example, a ferroelectric memory to read and write data in a memory capacitor MC. SOLUTION: A main reference bit line/BL0 is connected to reference voltage VREF through a charging switch element TL. The other reference bit line/BLi is connected to the main bit line/BL0 through a balance adjusting switch element TA for electric charges balance adjustment between parasitic capacitance of each reference bit line. At the time, reference voltage VGEN is separated from the main reference bit line/BL0, other reference bit lines /BL1, /BL2, /BL3 are connected to the main reference bit line in parallel. Thereby, balance adjustment of electric charges accumulated in parasitic capacitance CPi of each reference bit line connected in parallel is performed, reference voltage VREF is distributed as equal plural bit line reference voltage V/BLi.

    CURRENT DRIVE CIRCUIT FOR MRAM
    3.
    发明专利
    CURRENT DRIVE CIRCUIT FOR MRAM 审中-公开

    公开(公告)号：JP2002093144A

    公开(公告)日：2002-03-29

    申请号：JP2001197558

    申请日：2001-06-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  GOGL DIETMAR ,  MUELLER GERHARD ,  LOEER THOMAS

    IPC: G11C11/14 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

    Abstract: PROBLEM TO BE SOLVED: To provide a current driver arrangement capable of supplying a large current at a low voltage when the area needs to be small. SOLUTION: In a current driver arrangement described in the above, this problem can be solved by configuring a driver of an n-type field effect transistor and a current source connected in series therewith. Concretely, a current driver arrangement for an MRAM is provided comprising a memory cell field having a plurality of memory cells (Z) at the crossing position of a word line (WL) and a bit line (BL), and drivers (T1, T2) supplied to each end of the above word line (WL) and the above bit line (BL), and allocated to the above word line (WL) and the above bit line (BL).

    INTEGRATED CIRCUIT MEMORY
    4.
    发明专利
    INTEGRATED CIRCUIT MEMORY 失效

    公开(公告)号：JP2000331474A

    公开(公告)日：2000-11-30

    申请号：JP2000130113

    申请日：2000-04-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ZORUTAN MANYOOKI ,  ROEHR THOMAS ,  BOEHM THOMAS

    IPC: G11C14/00 ,  G11C7/06 ,  G11C7/10 ,  G11C11/22

    Abstract: PROBLEM TO BE SOLVED: To reduce power consumption under an area required for column selection line path by connecting each bit line to a sense amplifier to which a bit line belongs through a first switching element, and connecting each bit line to a standby potential through a second switching element. SOLUTION: All column selection lines LCSLK takes a low potential so far as any column is not selected out of plural columns. Consequently, a first transistor A is made non-conduction state, and a second transistor B is conducted. Therefore, bit lines BL , bBL at the edge of cellfield AR are decoupled to a sense amplifier SA, and are in a standby potential VSTB. Consequently, a selection transistor T of a memory cell MC is made a non- conduction state. Thereby, contents of a memory of the memory cell MC is not affected at the time of access.

    MRAM MODULE STRUCTURE
    5.
    发明专利
    MRAM MODULE STRUCTURE 审中-公开

    公开(公告)号：JP2002164515A

    公开(公告)日：2002-06-07

    申请号：JP2001275812

    申请日：2001-09-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  GOGL DIETMAR ,  FREITAG MARTIN ,  LAMMERS STEFAN

    IPC: G11C11/14 ,  G11C5/02 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

    Abstract: PROBLEM TO BE SOLVED: To provide an MRAM module structure wherein high packing density of memory cell sections is achieved. SOLUTION: This MRAM module structure is constituted of a plurality of memory cell sections (A, P). The respective memory cell sections (A, P) are constituted of memory arrays (A) having a plurality of memory cells (WML, TL, HML) and peripheral circuits (P) surrounding edges of the memory arrays (A). The peripheral circuits (P) surround the memory arrays (A) in such a manner that the respective memory cell sections (A, P) have a cross structure in a plane, essentially. The memory cell sections (A, P) are so nested in each other that the memory cell sections (A, P) are offset mutually on individual rows (1, 2, 3).

    ELECTRONIC DRIVER CIRCUIT
    6.
    发明专利
    ELECTRONIC DRIVER CIRCUIT 审中-公开

    公开(公告)号：JP2002133855A

    公开(公告)日：2002-05-10

    申请号：JP2001241347

    申请日：2001-08-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  ROEHR THOMAS ,  GOGL DIETMAR

    IPC: G11C11/14 ,  G11C8/08 ,  G11C8/10 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

    Abstract: PROBLEM TO BE SOLVED: To reduce the complexity and occupancy area of wirings in a driver circuit for word lines of a memory matrix. SOLUTION: In the electronic driver circuit for the word lines WL in the memory matrix 3, a driver source 2, for example, coded output sides IV0-IV3 of a current/voltage source are connected to selected word lines WLi-2-WLi+1. In this case, the word lines WL are selected for every block by control signals SLNP, SLN1, SLN2, and the outputs of the driver source 2 are applied to them. In that case, each activated word line WLi is selected by the coding of the driver source 2.

    INTEGRATED SEMICONDUCTOR MEMORY
    7.
    发明专利
    INTEGRATED SEMICONDUCTOR MEMORY 失效

    公开(公告)号：JP2001273791A

    公开(公告)日：2001-10-05

    申请号：JP2001029947

    申请日：2001-02-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  HOENIGSCHMID HEINZ ,  LAMMERS STEFAN ,  MANYOKI ZOLTAN

    IPC: G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

    Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor memory constituted so that a redundant memory cell unit can be tested and the circuit configuration therefor is scarcely complexed inevitably. SOLUTION: This memory is provided with a memory cell MC arranged as a normal unit WL being addressable, a memory cell MC arranged as at least one unit RWL1 to replace the normal unit, an address bus 3 to which an address ADR can be applied, a redundant circuit 1 for selecting a redundant unit RWL1 connected to this address bus 3, and a processing unit 2. The processing unit 2 is connected to a terminal A of the address bus 3 at an input side, and connected to an input side of the redundant circuit 1 at an output side. The redundant unit RWL1 can be tested before programming of restoration information in the redundant circuit 1, moreover, the circuit is not made complex so much.

    Integrated memory having a bit line reference voltage, and a method for producing the bit line reference voltage
    8.
    发明授权
    Integrated memory having a bit line reference voltage, and a method for producing the bit line reference voltage 失效
    具有位线参考电压的集成存储器，以及用于产生位线参考电压的方法

    公开(公告)号：US6347059B2

    公开(公告)日：2002-02-12

    申请号：US81692501

    申请日：2001-03-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  MANYOKI ZOLTAN ,  ESTERL ROBERT ,  ROEHR THOMAS

    IPC: G11C11/22 ,  G11C7/02

    CPC classification number: G11C11/22

    Abstract: A semiconductor memory, in particular a ferroelectric semiconductor memory, has a differential write/read amplifier which is connected, via transfer transistors, to a bit line pair. The bit line pair includes a bit line and a corresponding reference bit line. The differential write/read amplifier is for reading data from and writing data to the memory capacitor (MC). In order to improve the accuracy of the bit line reference voltage, a main reference bit line is connected, via a charge switching element, to a reference voltage. At least one further reference bit line is connected to the main reference bit line via an equalization switching element for charge equalization between the reference bit lines.

    Abstract translation: 半导体存储器，特别是铁电半导体存储器，具有通过传输晶体管连接到位线对的差分写/读放大器。 位线对包括位线和对应的参考位线。 差分写/读放大器用于从存储电容（MC）读取数据并将数据写入存储电容（MC）。 为了提高位线参考电压的精度，主参考位线经由充电开关元件连接到参考电压。 至少一个另外的参考位线通过用于参考位线之间的电荷均衡的均衡开关元件连接到主参考位线。

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