公开(公告)号：AT518240T

公开(公告)日：2011-08-15

申请号：AT00101726

申请日：2000-01-27

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HO HERBERT ,  SRINIVASAN RADHIKA ,  HAMMERL ERWIN ,  AGAHI FARID ,  BRONNER GARY ,  FLIETNER BERTRAND

IPC: H01L21/76 ,  H01L21/762

Abstract: A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an insulating oxide layer prior to deposition of the silicon nitride liner. Preferably, the insulating oxide layer comprises tetraethylorthosilicate. The method comprises of etching one or more shallow trench isolations into a semiconductor wafer; depositing an insulating oxide layer into the trench; growing a thermal oxide in the trench; and depositing a silicon nitride liner in the trench. The thermal oxide may be grown prior to or after deposition of the insulating oxide layer.

公开(公告)号：DE69939573D1

公开(公告)日：2008-10-30

申请号：DE69939573

申请日：1999-11-16

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： FLIETNER BERTRAND ,  MULLER K PAUL

IPC: G05B19/00 ,  H01L21/66 ,  G05D23/00 ,  H01L23/544

Abstract: A measurement device for in-situ measurement of processing parameters, in accordance with the present invention, includes a semiconductor wafer having at least one processed chip formed thereon. The processed chip further includes at least one sensor for measuring process parameters. A memory storage device for storing the process parameters as the process parameters are measured by the at least one sensor is also included. A timing device is provided for tracking the process parameters as a function of time, and a power supply is included for providing power to the at least one sensor, the memory storage device and the timing device. Also, a method is described for making measurements with the measurement device.

公开(公告)号：DE69827732D1

公开(公告)日：2004-12-30

申请号：DE69827732

申请日：1998-09-17

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MULLER KARL P ,  FLIETNER BERTRAND ,  ROITHNER KLAUS

IPC: H01L21/302 ,  H01J37/32 ,  H01L21/3065 ,  C23C16/44

Abstract: A gas distribution plate (60) for a semiconductor processing chamber (86) includes a gas distribution plate for distributing gases across a surface of a semiconductor wafer (84) to be processed in the chamber. The gas distribution plates has a substantially planar member having gas outlets for distributing a reactant gas across the surface of the semiconductor wafer, the gas outlet means includes a plurality of apertures (66) defined in said planar member, the plurality of apertures having different areas at predetermined locations to adjust etching gas flow. A pump (80) is provided for evacuating a reactant-product gas created across the surface of the semiconductor wafer during wafer processing. The pump (80) includes a plurality of tubes extending through the planar member, the plurality of tubes having apertures, and the apertures have different areas at predetermined locations to adjust reactant gas and reactant-product gas flow wherein the gas outlets and the pump coact to substantially maintain a predetermined concentration of the reactant gas and a predetermined concentration of the reactant-product gas across the surface of the semiconductor wafer during wafer processing.

公开(公告)号：DE69827732T2

公开(公告)日：2005-11-24

申请号：DE69827732

申请日：1998-09-17

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MULLER KARL P ,  FLIETNER BERTRAND ,  ROITHNER KLAUS

IPC: H01L21/302 ,  H01J37/32 ,  H01L21/3065 ,  C23C16/44

Abstract: A gas distribution plate (60) for a semiconductor processing chamber (86) includes a gas distribution plate for distributing gases across a surface of a semiconductor wafer (84) to be processed in the chamber. The gas distribution plates has a substantially planar member having gas outlets for distributing a reactant gas across the surface of the semiconductor wafer, the gas outlet means includes a plurality of apertures (66) defined in said planar member, the plurality of apertures having different areas at predetermined locations to adjust etching gas flow. A pump (80) is provided for evacuating a reactant-product gas created across the surface of the semiconductor wafer during wafer processing. The pump (80) includes a plurality of tubes extending through the planar member, the plurality of tubes having apertures, and the apertures have different areas at predetermined locations to adjust reactant gas and reactant-product gas flow wherein the gas outlets and the pump coact to substantially maintain a predetermined concentration of the reactant gas and a predetermined concentration of the reactant-product gas across the surface of the semiconductor wafer during wafer processing.

公开(公告)号：DE69929266D1

公开(公告)日：2006-03-30

申请号：DE69929266

申请日：1999-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MICHAELIS ALEXANDER ,  RANADE RAJIV ,  FLIETNER BERTRAND

IPC: H01L21/302 ,  H01L29/94 ,  H01L21/02 ,  H01L21/30 ,  H01L21/3065 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: A vertical trench in a silicon wafer for use in forming the storage capacitor of a DRAM is etched by reactive ion etching in a manner to have a profile that has multiple waists. This profile is obtained by varying the rate of flow of coolant in the base member on which the silicon wafer is supported during the reactive ion etching to vary the temperature of the silicon wafer during the etching. Alternatively, the multiple waists are achieved by either by varying the ratio of the different gases in the etching chamber or the total gas pressure in the chamber.

公开(公告)号：DE69929266T2

公开(公告)日：2006-08-17

申请号：DE69929266

申请日：1999-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MICHAELIS ALEXANDER ,  RANADE RAJIV ,  FLIETNER BERTRAND

IPC: H01L21/302 ,  H01L29/94 ,  H01L21/02 ,  H01L21/30 ,  H01L21/3065 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: A vertical trench in a silicon wafer for use in forming the storage capacitor of a DRAM is etched by reactive ion etching in a manner to have a profile that has multiple waists. This profile is obtained by varying the rate of flow of coolant in the base member on which the silicon wafer is supported during the reactive ion etching to vary the temperature of the silicon wafer during the etching. Alternatively, the multiple waists are achieved by either by varying the ratio of the different gases in the etching chamber or the total gas pressure in the chamber.

公开(公告)号：JP2000228442A

公开(公告)日：2000-08-15

申请号：JP2000025509

申请日：2000-02-02

Applicant: IBM ,  SIEMENS AG

Inventor： HO HERBERT ,  SRINIVASAN RADHIKA ,  HAMMERL ERWIN ,  AGAHI FARID ,  BRONNER GARY ,  FLIETNER BERTRAND

IPC: H01L21/76 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To reduce parasitic leak of a shallow trench isolation via. SOLUTION: A distance between a silicon nitride liner 43 and an active silicon sidewall is increased by depositing an insulation oxide layer 20 prior to depositing of the silicon nitride liner 43. Preferably, the insulation oxide layer 20 comprises tetraethyl orthosilicate. The method includes formation of one or a plurality of shallow trench isolations inside a semiconductor wafer through etching, sticking of an insulation oxide layer 20 inside a trench, formation of thermal oxide 25 inside a trench and sticking of the silicon nitride liner 43 inside a trench. The thermal oxide 25 can be formed before or after the insulation oxide layer 20 is deposited.

公开(公告)号：JP2000174084A

公开(公告)日：2000-06-23

申请号：JP32522699

申请日：1999-11-16

Applicant: SIEMENS AG ,  IBM

Inventor： FLIETNER BERTRAND ,  K PAUL MULLER

IPC: G05B19/00 ,  G05D23/00 ,  H01L21/66 ,  H01L23/544

Abstract: PROBLEM TO BE SOLVED: To enhance a manufacturing yield in a semiconductor manufacture by a method wherein process parameters are measured by a sensor and are stored in a storage device, and also the process parameters are traced by a timing device as a temporal function. SOLUTION: A semiconductor wafer 10 is fitted on a chamber in order to inspect a manufacture process, and various process parameters are measured by a sensor 14 provided in a region such as an end part 16 of the wafer 10, a center part of the wafer 10, or the like with respect to uniformity of the entire wafer 10 during the process, and the measured process parameters are stored in a storage device. Furthermore, data of the process parameters are read out via a data interface 32, and the process parameters are traced by a plurality of timing devices having a power source as a temporal function. Thereby, it is possible to enhance a manufacturing yield in a semiconductor manufacture.

公开(公告)号：JPH11154667A

公开(公告)日：1999-06-08

申请号：JP26681398

申请日：1998-09-21

Applicant: SIEMENS AG ,  IBM

Inventor： MULLER KARL P ,  FLIETNER BERTRAND ,  ROITHNER KLAUS

IPC: H01L21/302 ,  H01J37/32 ,  H01L21/3065

Abstract: PROBLEM TO BE SOLVED: To substantially reduce etching nonuniformity between center and edge of a semiconductor wafer, by providing gas distribution plates for a semiconductor treating chamber, including a plate for distributing a gas over the surface of the wafer to be treated in this chamber. SOLUTION: A gas distribution plate includes an upper and a lower plates 62, 64 disposed with a spacing to define a space or manifold 72. Mutually spaced cylindrical pipes 68 extend through the space 72 between the upper and lower plates 62, 64 to define gas jet passages 69. Mutually spaced gas inlet apertures 70 are formed in a tubular space 71 extending between the upper and the lower plates 62, 64. The lower plate 64 includes mutually spaced gas outlet apertures 66. An exhaust pump controls the etching gas pressure between the upper and the lower plates 62, 64.