公开(公告)号：DE19841893B4

公开(公告)日：2005-06-30

申请号：DE19841893

申请日：1998-09-11

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： FLECK ROD G ,  MATTHEIS KARL-HEINZ

IPC: G06F9/30 ,  G06F9/305

公开(公告)号：DE19940611B4

公开(公告)日：2009-06-18

申请号：DE19940611

申请日：1999-08-27

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： MATTHEIS KARL-HEINZ ,  BACIGALUPO TOMMASO

IPC: G06F11/27 ,  G06F11/22 ,  G06F11/267

Abstract: A method and system for accurately indicating test results from testing routines of a self-check operation during initialization or reset of the system utilize test result bits in a secure status register that must be sequentially reset to indicate a successful completion of the self-check operation. The system is a microcontroller that can be incorporated into various consumer products requiring digital processing. Each test result bit represents a distinct component of the system that is tested during the self-check operation. The test result bits in the status register can only be reset one at a time, by activating a demultiplexer which resets a particular test result bit in response to a successful testing of a component. However, the demultiplexer can only be activated by modifying a control bit in an access register that is protected by a double password scheme. To modify the control bit, the CPU must provide two valid passwords. The activation of the demultiplexer is repeated for each component of the system that is tested to reset a corresponding test result bit in the status register. Consequently, the CPU must write a different device designation value into the control register for each component that is tested. When all the test result bits have been reset, a confirmation signal is generated.

公开(公告)号：DE69803860D1

公开(公告)日：2002-03-21

申请号：DE69803860

申请日：1998-09-04

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： MATTHEIS KARL-HEINZ ,  ROHM PETER

IPC: G06F13/28

Abstract: Th present invention relates to a DMA-controller having a definable plurality of transfer channels. According to the present invention such a unit comprises a data processing unit with a bus interface unit being coupled with a bus for transferring data. The data processing unit executes a data transfer on said bus dependent on programmable parameters. It further comprises a parameter memory storing those parameters for each transfer channel, whereby the parameter memory provides a first memory area which stores for each defined transfer channel a word comprising a vector address to a second memory area comprising specific parameters for said transfer channel.

公开(公告)号：DE19940611A1

公开(公告)日：2000-03-30

申请号：DE19940611

申请日：1999-08-27

Applicant: INFINEON TECHNOLOGIES CORP SAN

Inventor： MATTHEIS KARL-HEINZ ,  BACIGALUPO TOMMASO

IPC: G06F11/22 ,  G06F11/267

Abstract: The method involves producing a confirmation signal to indicate that each component has successfully completed a self test, only when all bit in an N-bit field have been reset. The method involves conducting a self-test process on a selected, predefined component of the system to determine whether it can operate according to a defined protocol. A defined value is written into a device naming field of a first register, in response to a positive determination in respect of the self-test process for the selected component. The defined value is associated with the selected component. A first bit in an N-bit field is selectively reset, in a second register, in response to the naming field, where N is greater than 1 and the first bit is positively associated with the selected component. A confirmation signal is produced to indicate that each predefined component has successfully completed a selected self-test procedure, only if all bits in the N-bit field have been reset. An Independent claim is also included for a processing system with a self-test capability.

公开(公告)号：DE69803860T2

公开(公告)日：2002-10-02

申请号：DE69803860

申请日：1998-09-04

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： MATTHEIS KARL-HEINZ ,  ROHM PETER

IPC: G06F13/28

Abstract: Th present invention relates to a DMA-controller having a definable plurality of transfer channels. According to the present invention such a unit comprises a data processing unit with a bus interface unit being coupled with a bus for transferring data. The data processing unit executes a data transfer on said bus dependent on programmable parameters. It further comprises a parameter memory storing those parameters for each transfer channel, whereby the parameter memory provides a first memory area which stores for each defined transfer channel a word comprising a vector address to a second memory area comprising specific parameters for said transfer channel.