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    DATA PROCESSOR HAVING MEMORY COUPLING UNIT
    1.
    发明专利
    DATA PROCESSOR HAVING MEMORY COUPLING UNIT 失效

    公开(公告)号：JP2000231535A

    公开(公告)日：2000-08-22

    申请号：JP32395199

    申请日：1999-11-15

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： FLECK ROD G ,  OBERLAENDER KLAUS ,  BAROR GIGY ,  EDER ALFRED ,  NGUYEN LE TRONG

    IPC: G06F9/30 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16

    Abstract: PROBLEM TO BE SOLVED: To provide a data processing unit which has a coupling unit for data transfer. SOLUTION: This data processing unit is provided with a register file 8 having plural registers, a memory having plural n-bit input/output ports, a coupling unit for connecting the memory to the register file and a memory address and a selection unit 9 for addressing a memory bank. The coupling unit includes at least a bus which forms 1st and 2nd sub buses and has at least 2n-bit bus width, a 1st coupler for selectively connecting each memory bank or register file to one of the sub buses and a 2nd coupler for connecting the register file or a memory bank to the buses.

    METHOD AND DEVICE FOR REDUCING INSTRUCTION TRANSACTION IN MICROPROCESSOR
    2.
    发明专利
    METHOD AND DEVICE FOR REDUCING INSTRUCTION TRANSACTION IN MICROPROCESSOR 失效

    公开(公告)号：JP2001005660A

    公开(公告)日：2001-01-12

    申请号：JP2000157106

    申请日：2000-05-26

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： SINGH BALRAJ ,  MATTELA VENKAT ,  CHESTERS ERIC ,  FLECK ROD G

    IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38

    Abstract: PROBLEM TO BE SOLVED: To make increasable the instruction issue bus bandwidth without increasing the size of a cache memory by selectively storing instructions in the cache memory related to a corresponding function unit. SOLUTION: A 1st instruction is fetched from a memory and it is judged whether its PS matches with one of entries of a tag PC cache (S502, 504). When the tag PC of the fetched instruction matches with one of the entries of one of tag PC caches, the PC of the fetched instruction is updated into a matching target PC specified in a cache memory (S504, 514). When a target instruction is stored in the fetched instruction, the target instruction is fetched from a program memory (S516, 518), but when the target instruction is stored in the fetched instruction, the target instruction is not requested of a programming memory; and a target operation code is injected into a target function unit (S520) in either case together with the target instruction.

    Data processing unit with interface for sharing registers by a processor and a coprocessor
    3.
    发明授权
    Data processing unit with interface for sharing registers by a processor and a coprocessor 有权
    具有用于由处理器和协处理器共享寄存器的接口的数据处理单元

    公开(公告)号：US6434689B2

    公开(公告)日：2002-08-13

    申请号：US18911198

    申请日：1998-11-09

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： FLECK ROD G ,  ARNOLD ROGER D ,  HOLMER BRUCE ,  LEMAY DANIELLE G

    IPC: G06F9/38 ,  G06F15/00

    CPC classification number: G06F9/3897 ,  G06F9/3877 ,  G06F9/3885

    Abstract: An apparatus is described that comprises a data processing unit and at least one coprocessor. The data processing unit comprises a register file having registers, a memory, a plurality of execution units, a coprocessor interface for coupling the at least one coprocessor with the data processing unit, and a pipeline configuration for processing instructions having a fetch stage for fetching an instruction from the memory, a decode stage for decoding an operational code from the instruction, an execution stage for activating one of the execution units, and a write-back stage for God writing back from the execution unit. The data processing unit comprises read-and write-lines coupling the register file with the coprocessor for exchanging operands, at least one control line indicating that the coprocessor is busy, and a plurality of control lines from the decode stage for controlling the coprocessor which are operated upon detection of a coprocessor instruction. The coprocessor is using the registers from the register file during execution of the coprocessor instruction. The coprocessor comprises a decode unit for decoding the coprocessor instruction and a plurality of coprocessor execution units that share the decode unit, the decode unit selects one of the coprocessor execution units upon the coprocessor instruction, and the selected one of the coprocessor execution units performs the coprocessor instruction.

    Abstract translation: 描述了一种包括数据处理单元和至少一个协处理器的装置。 数据处理单元包括具有寄存器，存储器，多个执行单元，用于将至少一个协处理器与数据处理单元耦合的协处理器接口的寄存器文件，以及用于处理具有取出级的指令的流水线配置， 来自存储器的指令，用于从指令解码操作代码的解码级，用于激活执行单元中的一个的执行级，以及用于从执行单元写回的上一级的回写级。 数据处理单元包括将寄存器文件与协处理器耦合用于交换操作数的读和写行，指示协处理器忙的至少一个控制线以及来自用于控制协处理器的解码级的多条控制线 在检测到协处理器指令时进行操作。 在执行协处理器指令期间，协处理器正在使用寄存器文件中的寄存器。 协处理器包括用于解码协处理器指令的解码单元和共享解码单元的多个协处理器执行单元，解码单元在协处理器指令中选择一个协处理器执行单元，并且所选择的一个协处理器执行单元执行 协处理器指令

    8.
    发明专利
    未知

    公开(公告)号：DE69903704D1

    公开(公告)日：2002-12-05

    申请号：DE69903704

    申请日：1999-08-26

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： FLECK ROD G ,  ARNOLD ROGER D ,  HOLMER BRUCE K ,  LEMAY DANIELLE G

    IPC: G06F9/38

    Abstract: A data processing unit is described comprising a register file, a memory, a plurality of execution units, a pipeline configuration for processing instructions having a fetch stage for fetching an instruction from said memory, a decode stage for decoding an operational code from said instruction, an execution stage for activating one of said execution units, and a write-back stage for writing back from said execution unit, a coprocessor interface for coupling at least one coprocessor. The data processing unit has read- and write-lines coupling said register file with said coprocessor for exchanging operands, at least one control line indicating that said coprocessor is busy, a plurality of control lines from said decode stage for controlling said coprocessor which are operated upon detection of a coprocessor instruction, whereby said coprocessor is using said registers from said register file during execution of a coprocessor instruction.

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