公开(公告)号：WO0185392A3

公开(公告)日：2002-10-10

申请号：PCT/US0115205

申请日：2001-05-10

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LIN CHENTING ,  PLOESSL ROBERT

IPC: B24B20060101 ,  B24B7/24 ,  B24B37/04 ,  H01L21/302 ,  H01L21/304 ,  H01L21/321 ,  H01L21/461 ,  H01L21/768

CPC classification number: H01L21/3212 ,  H01L21/7684

Abstract: A two-step chemical mechanical polishing (CMP) process is provided to minimize (reduce) dishing of metal lines (17) in trenches in an insulation (oxide) layer (12) of each of a plurality of semiconductor wafers during fabrication thereof. For each wafer, the first step involves CMP of a metal layer (15) disposed on the oxide layer (12) and having a lower portion located in the trenches (13) for forming metal lines and an upper portioN (18) overlying the lower portion (16). The first step polishing uses a first polishing pad to remove the bulk of the metal layer upper portion (18) while generating concomitant CMP residue, and leaves a minimized (reduced) remainder of the metal layer upper portion (18) without dishing of the metal layer lower portion (16) in the trenches (13). The second step continues the CMP with a second polishing pad to remove the remainder of the metal layer upper portion (18) with minimized (reduced) dishing of the metal layer lower portion (16) to an extent providing the metal lines (17) as individual metal lines (17) in the trenches (13). Each wafer undergoes the first step polishing with the first polishing pad and then the second step polishing with the second polishing pad. The second polishing pad has at most a deficient content of prior accumulated concomitant CMP residue, e.g., is a relatively fresh (clean) polishing pad.

Abstract translation: 提供两步化学机械抛光（CMP）工艺以在其制造期间使多个半导体晶片的绝缘（氧化物）层（12）中的沟槽中的金属线（17）的凹陷最小化（减少）。 对于每个晶片，第一步骤包括设置在氧化物层（12）上的金属层（15）的CMP，并且具有位于沟槽（13）中的下部，用于形成金属线，并且覆盖下部的上端口（18） 部分（16）。 第一步抛光使用第一抛光垫去除金属层上部（18）的主体，同时产生伴随的CMP残留物，并且使金属层上部（18）的最小（减少）余数不会金属脱落 沟槽（13）中的下层部分（16）。 第二步是用第二抛光垫继续CMP，以金属层下部（16）的最小化（减少）凹陷将金属层上部（18）的剩余部分移至提供金属线（17）的程度，以作为 沟槽（13）中的各个金属线（17）。 每个晶片用第一抛光垫进行第一步抛光，然后用第二抛光垫抛光第二步。 第二抛光垫至多具有先前累积的伴随的CMP残留物的不足量，例如是相对新鲜的（干净的）抛光垫。

公开(公告)号：DE60126758T2

公开(公告)日：2007-12-06

申请号：DE60126758

申请日：2001-05-10

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LIN CHENTING ,  PLOESSL ROBERT

IPC: H01L21/321 ,  B24B20060101 ,  B24B7/24 ,  B24B37/04 ,  H01L21/302 ,  H01L21/304 ,  H01L21/461 ,  H01L21/768

Abstract: A two-step chemical mechanical polishing (CMP) process is provided to minimize (reduce) dishing of metal lines in trenches in an insulation (oxide) layer of each of a plurality of semiconductor wafers during fabrication thereof. For each wafer, the first step involves CMP of a metal layer disposed on the oxide layer and having a lower portion located in the trenches for forming metal lines and an upper portion overlying the lower portion. The first step polishing uses a first polishing pad to remove the bulk of the metal layer upper portion while generating concomitant CMP residue, and leaves a minimized (reduced) remainder of the metal layer upper portion without dishing of the metal layer lower portion in the trenches. The second step continues the CMP with a second polishing pad to remove the remainder of the metal layer upper portion with minimized (reduced) dishing of the metal layer lower portion to an extent providing the metal lines as individual metal lines in the trenches. Each wafer undergoes the first step polishing with the first polishing pad and then the second step polishing with the second polishing pad. The second polishing pad has at most a deficient content of prior accumulated concomitant CMP residue, e.g., is a relatively fresh (clean) polishing pad.

公开(公告)号：DE60126758D1

公开(公告)日：2007-04-05

申请号：DE60126758

申请日：2001-05-10

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LIN CHENTING ,  PLOESSL ROBERT

IPC: H01L21/321 ,  B24B20060101 ,  B24B7/24 ,  B24B37/04 ,  H01L21/302 ,  H01L21/304 ,  H01L21/461 ,  H01L21/768

Abstract: A two-step chemical mechanical polishing (CMP) process is provided to minimize (reduce) dishing of metal lines in trenches in an insulation (oxide) layer of each of a plurality of semiconductor wafers during fabrication thereof. For each wafer, the first step involves CMP of a metal layer disposed on the oxide layer and having a lower portion located in the trenches for forming metal lines and an upper portion overlying the lower portion. The first step polishing uses a first polishing pad to remove the bulk of the metal layer upper portion while generating concomitant CMP residue, and leaves a minimized (reduced) remainder of the metal layer upper portion without dishing of the metal layer lower portion in the trenches. The second step continues the CMP with a second polishing pad to remove the remainder of the metal layer upper portion with minimized (reduced) dishing of the metal layer lower portion to an extent providing the metal lines as individual metal lines in the trenches. Each wafer undergoes the first step polishing with the first polishing pad and then the second step polishing with the second polishing pad. The second polishing pad has at most a deficient content of prior accumulated concomitant CMP residue, e.g., is a relatively fresh (clean) polishing pad.