公开(公告)号：JP2000280166A

公开(公告)日：2000-10-10

申请号：JP2000078478

申请日：2000-03-21

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LIN CHENTING ,  VAN DEN BERG ROBERT ,  PANDEY SUMIT

IPC: B24B37/04 ,  B24B57/02 ,  H01L21/302 ,  H01L21/304 ,  B24B37/00

Abstract: PROBLEM TO BE SOLVED: To even the distribution of the slurry during the polishing by distributing the slurry from plural positions onto a polishing cloth. SOLUTION: A multi-position slurry dispenser 242 has a discharge pipe, and this discharge pipe has plural outlets 248 formed in the discharge pipe. The discharge pipe can be formed into a cylindrical shape. The discharge pipe is positioned along the radius of a polishing cloth. The slurry is distributed onto the polishing cloth 246 through outlets. The slurry is distributed to various parts of the polishing cloth 246 by having plural outlets, and distribution of the slurry capable of being controlled more for improvement of the CMP process is generated. The multi-position dispenser is optimally used in response to a set of an operation parameter and/or expendable supplies so as to form a slurry profile for generating a desirable polishing characteristic.

公开(公告)号：WO02054457A2

公开(公告)日：2002-07-11

申请号：PCT/US0143904

申请日：2001-11-14

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LIAN JINGYU ,  LIN CHENTING ,  NAGEL NICOLAS ,  WISE MICHAEL

IPC: H01L21/02

CPC classification number: H01L28/75 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  Y10S257/906 ,  Y10S257/908

Abstract: A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive liner (240) and a second conductive liner (242). First conductive layer (240) comprises Pt, and second conductive liner (242) comprises a thin layer of conductive oxide. The multi-layer electrode (246) prevents oxygen diffusion through the top conductive region (244) and reduces material variation during electrode patterning.

Abstract translation: 一种多层电极（246）及其制造方法，其中通过第一导电衬垫（240）和第二导电衬套（242）将导电区域（244）与阻挡层（222）分离。 第一导电层（240）包括Pt，并且第二导电衬垫（242）包括导电氧化物的薄层。 多层电极（246）防止氧扩散通过顶部导电区域（244）并且减少电极图案化期间的材料变化。

公开(公告)号：WO0185392A3

公开(公告)日：2002-10-10

申请号：PCT/US0115205

申请日：2001-05-10

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LIN CHENTING ,  PLOESSL ROBERT

IPC: B24B20060101 ,  B24B7/24 ,  B24B37/04 ,  H01L21/302 ,  H01L21/304 ,  H01L21/321 ,  H01L21/461 ,  H01L21/768

CPC classification number: H01L21/3212 ,  H01L21/7684

Abstract: A two-step chemical mechanical polishing (CMP) process is provided to minimize (reduce) dishing of metal lines (17) in trenches in an insulation (oxide) layer (12) of each of a plurality of semiconductor wafers during fabrication thereof. For each wafer, the first step involves CMP of a metal layer (15) disposed on the oxide layer (12) and having a lower portion located in the trenches (13) for forming metal lines and an upper portioN (18) overlying the lower portion (16). The first step polishing uses a first polishing pad to remove the bulk of the metal layer upper portion (18) while generating concomitant CMP residue, and leaves a minimized (reduced) remainder of the metal layer upper portion (18) without dishing of the metal layer lower portion (16) in the trenches (13). The second step continues the CMP with a second polishing pad to remove the remainder of the metal layer upper portion (18) with minimized (reduced) dishing of the metal layer lower portion (16) to an extent providing the metal lines (17) as individual metal lines (17) in the trenches (13). Each wafer undergoes the first step polishing with the first polishing pad and then the second step polishing with the second polishing pad. The second polishing pad has at most a deficient content of prior accumulated concomitant CMP residue, e.g., is a relatively fresh (clean) polishing pad.

Abstract translation: 提供两步化学机械抛光（CMP）工艺以在其制造期间使多个半导体晶片的绝缘（氧化物）层（12）中的沟槽中的金属线（17）的凹陷最小化（减少）。 对于每个晶片，第一步骤包括设置在氧化物层（12）上的金属层（15）的CMP，并且具有位于沟槽（13）中的下部，用于形成金属线，并且覆盖下部的上端口（18） 部分（16）。 第一步抛光使用第一抛光垫去除金属层上部（18）的主体，同时产生伴随的CMP残留物，并且使金属层上部（18）的最小（减少）余数不会金属脱落 沟槽（13）中的下层部分（16）。 第二步是用第二抛光垫继续CMP，以金属层下部（16）的最小化（减少）凹陷将金属层上部（18）的剩余部分移至提供金属线（17）的程度，以作为 沟槽（13）中的各个金属线（17）。 每个晶片用第一抛光垫进行第一步抛光，然后用第二抛光垫抛光第二步。 第二抛光垫至多具有先前累积的伴随的CMP残留物的不足量，例如是相对新鲜的（干净的）抛光垫。

公开(公告)号：WO0199182A3

公开(公告)日：2002-04-18

申请号：PCT/US0119820

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： WEBER STEFAN ,  RUF ALEXANDER ,  LIN CHENTING ,  KNORR ANDREAS

IPC: H01L21/285 ,  H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/28568 ,  H01L21/76807 ,  H01L21/76871 ,  H01L21/76877

Abstract: A method for forming metallizations for semiconductor devices, in accordance with the present invention, includes forming trenches (107) in a dielectric layer (104), depositing a single layer diffusion barrier (116) in the trenches, and without an air-brake, depositing a seed layer (118) of metal on the surface of the diffusion barrier. The trenches are then filled with metal (120). The metal adheres to the seed layer, which adheres to the diffusion barrier to provide many improvements in electrical characteristics as well as to reduce failures in the semiconductor devices.

Abstract translation: 根据本发明的用于形成用于半导体器件的金属化的方法包括在电介质层（104）中形成沟槽（107），在沟槽中沉积单层扩散阻挡层（116），并且没有空气制动， 在扩散阻挡层的表面上沉积金属种子层（118）。 然后用金属（120）填充沟槽。 金属粘附到种子层，其粘附到扩散阻挡层，以提供许多电特性的改进以及减少半导体器件的故障。

公开(公告)号：DE60126758D1

公开(公告)日：2007-04-05

申请号：DE60126758

申请日：2001-05-10

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LIN CHENTING ,  PLOESSL ROBERT

IPC: H01L21/321 ,  B24B20060101 ,  B24B7/24 ,  B24B37/04 ,  H01L21/302 ,  H01L21/304 ,  H01L21/461 ,  H01L21/768

Abstract: A two-step chemical mechanical polishing (CMP) process is provided to minimize (reduce) dishing of metal lines in trenches in an insulation (oxide) layer of each of a plurality of semiconductor wafers during fabrication thereof. For each wafer, the first step involves CMP of a metal layer disposed on the oxide layer and having a lower portion located in the trenches for forming metal lines and an upper portion overlying the lower portion. The first step polishing uses a first polishing pad to remove the bulk of the metal layer upper portion while generating concomitant CMP residue, and leaves a minimized (reduced) remainder of the metal layer upper portion without dishing of the metal layer lower portion in the trenches. The second step continues the CMP with a second polishing pad to remove the remainder of the metal layer upper portion with minimized (reduced) dishing of the metal layer lower portion to an extent providing the metal lines as individual metal lines in the trenches. Each wafer undergoes the first step polishing with the first polishing pad and then the second step polishing with the second polishing pad. The second polishing pad has at most a deficient content of prior accumulated concomitant CMP residue, e.g., is a relatively fresh (clean) polishing pad.

公开(公告)号：DE60126758T2

公开(公告)日：2007-12-06

申请号：DE60126758

申请日：2001-05-10

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LIN CHENTING ,  PLOESSL ROBERT

IPC: H01L21/321 ,  B24B20060101 ,  B24B7/24 ,  B24B37/04 ,  H01L21/302 ,  H01L21/304 ,  H01L21/461 ,  H01L21/768

Abstract: A two-step chemical mechanical polishing (CMP) process is provided to minimize (reduce) dishing of metal lines in trenches in an insulation (oxide) layer of each of a plurality of semiconductor wafers during fabrication thereof. For each wafer, the first step involves CMP of a metal layer disposed on the oxide layer and having a lower portion located in the trenches for forming metal lines and an upper portion overlying the lower portion. The first step polishing uses a first polishing pad to remove the bulk of the metal layer upper portion while generating concomitant CMP residue, and leaves a minimized (reduced) remainder of the metal layer upper portion without dishing of the metal layer lower portion in the trenches. The second step continues the CMP with a second polishing pad to remove the remainder of the metal layer upper portion with minimized (reduced) dishing of the metal layer lower portion to an extent providing the metal lines as individual metal lines in the trenches. Each wafer undergoes the first step polishing with the first polishing pad and then the second step polishing with the second polishing pad. The second polishing pad has at most a deficient content of prior accumulated concomitant CMP residue, e.g., is a relatively fresh (clean) polishing pad.