PATTERNING PROCESS AND LITHOGRAPHIC METHOD FOR SEMICONDUCTOR WAFERS AND SEMICONDUCTOR WAFER PATTERNING APPARATUS

    公开(公告)号:JP2002313717A

    公开(公告)日:2002-10-25

    申请号:JP2002062283

    申请日:2002-03-07

    Abstract: PROBLEM TO BE SOLVED: To provide a patterning process and a patterning apparatus which avoid restrictions in mask inspections and problems at alignment and compensates the line shortening, the problem in the prior part. SOLUTION: The process comprises a step of covering a wafer surface with a mask and a step of transferring a mask pattern to the wafer surface with a specified magnification. In the step of transferring the mask pattern the wafer is moved horizontally at a first velocity, while the mask is moved horizontally at a second velocity to expose a part of the wafer surface wherein the first and second velocities differ from each other and the ratio of the first velocity to the second velocity is different from the magnifying power.

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