公开(公告)号：DE10261330A1

公开(公告)日：2003-08-14

申请号：DE10261330

申请日：2002-12-27

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  KUDELKA STEPHAN P ,  SCHROEDER UWE ,  MCSTAY IRENE LENNOX ,  RAHN STEPHEN

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8242

Abstract: In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not shrink with decreasing groundrule/cell size, comprising:a) providing a semiconductor substrate having a collar region and an adjacent region below the collar region, the collar region having SiO deposited thereon;b) depositing a SiN liner on said collar region and on the region below the collar;c) depositing a layer of a-Si on the SiN liner to form a micromask;d) subjecting the structure from step c) to an anneal/oxidation step under a wet environment at a sufficient temperature to form a plurality of oxide dot hardmasks;e) subjecting the SiN liner to an etch selective to SiO;f) subjecting the structure from step e) to a Si transfer etch using a chemical dry etch (CDE) selective to SiO to create rough Si surface;g) stripping SiO and the SiN; and forming a node and collar deposition.