公开(公告)号：WO02086904A2

公开(公告)日：2002-10-31

申请号：PCT/US0210892

申请日：2002-04-08

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUDELKA STEPHAN P ,  JAIPRAKASH VENKATACHAIAM C ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242 ,  G11C11/00

CPC classification number: H01L27/10864 ,  H01L27/10876 ,  H01L27/10888

Abstract: A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.

Abstract translation: 存储单元的方法具有沟槽电容器和与电容器相邻的垂直晶体管。 垂直晶体管在沟槽电容器上方具有栅极导体。 栅极导体的上部比栅极导体的下部窄。 存储单元还包括邻近栅极导体的上部的间隔物和邻近栅极导体的位线接触。 间隔物减少了位线接触和栅极导体之间​​的短路。 栅极导体上方的栅极接触具有将栅极接触与位线分离的绝缘体。 栅极导体的上部和下部的宽度之间的差异减小了位线接触和栅极导体之间​​的短路。

公开(公告)号：WO0193323A3

公开(公告)日：2002-06-27

申请号：PCT/US0115997

申请日：2001-05-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NAEEM MUNIR D ,  LEE BRIAN S ,  MATHAD GANGADHARA S ,  LEE HEON ,  KIM BYEONG YEOL ,  MORALES ELIZABETH ,  KUDELKA STEPHAN P ,  RANADE RAJIV ,  PARK YOUNG-JIN

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/311 ,  H01L21/8239

CPC classification number: H01L21/3081 ,  H01L21/3065

Abstract: A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., > 30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid. The controlled thickness of the film allows achieving a predetermined DT depth for high aspect ratio structures

Abstract translation: 最小化RIE滞后的方法（即，在使用侧壁膜沉积的沟槽开口的构造期间产生的深沟槽（DT）的底部处的中性和离子通量））具有大纵横比的DRAM（即， > 30：1）。 该方法形成钝化膜，以防止基板的各向同性蚀刻所必需的程度，从而将所需的轮廓和DT的形状保持在基板内。 所述的RIE工艺提供了蚀刻到衬底中以实现预定深度的部分DT。 允许钝化膜生长到一定厚度，仍然低于其将关闭深沟槽的开口的程度。 或者，通过非RIE蚀刻工艺去除钝化膜。 可以用诸如氢氟酸（缓冲或非缓冲）的化学品或者使用蒸气相和/或非电离化学物质如无水氢氟酸来湿法蚀刻除去膜的非RIE工艺。 膜的受控厚度允许实现高纵横比结构的预定DT深度

公开(公告)号：DE10261330A1

公开(公告)日：2003-08-14

申请号：DE10261330

申请日：2002-12-27

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  KUDELKA STEPHAN P ,  SCHROEDER UWE ,  MCSTAY IRENE LENNOX ,  RAHN STEPHEN

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8242

Abstract: In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not shrink with decreasing groundrule/cell size, comprising:a) providing a semiconductor substrate having a collar region and an adjacent region below the collar region, the collar region having SiO deposited thereon;b) depositing a SiN liner on said collar region and on the region below the collar;c) depositing a layer of a-Si on the SiN liner to form a micromask;d) subjecting the structure from step c) to an anneal/oxidation step under a wet environment at a sufficient temperature to form a plurality of oxide dot hardmasks;e) subjecting the SiN liner to an etch selective to SiO;f) subjecting the structure from step e) to a Si transfer etch using a chemical dry etch (CDE) selective to SiO to create rough Si surface;g) stripping SiO and the SiN; and forming a node and collar deposition.

公开(公告)号：DE10239488A1

公开(公告)日：2003-07-03

申请号：DE10239488

申请日：2002-08-28

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： KUDELKA STEPHAN P ,  TEWS HELMUT HORST ,  GENZ OLIVER

IPC: H01L21/8242

Abstract: Production of a trench dynamic random access memory cell includes: forming pad nitride on substrate and ion etching trench; depositing nitride layer in trench; filling trench with polysilicon filling; back etching filling; forming nitrided oxide collar or oxide layer; ion etching; dissolving filling trench and nitride etching; extending trench; and forming trenched plate on trench side walls. Production of a trench dynamic random access memory (DRAM) cell in a semiconductor substrate comprises: forming a pad nitride on the surface of the substrate and ion etching a trench vertically to a first depth; depositing a nitride layer (20) in the trench; filling the trench with a polysilicon filling (21); back etching the filling to a collar depth; oxidizing to convert the exposed nitride layer into a nitrided oxide collar or depositing an oxide layer on the nitride layer; ion etching to open the base oxide; dissolving the filling trench and nitride etching selectively to the oxide; extending the trench in the horizontal direction by etching the lower trench side walls and the base during masking of the upper side walls; forming a trenched plate on the base of the trench side walls; forming a node dielectric in the trench; filling the trench with a polysilicon filling; back etching the filling; depositing a collar oxide; ion etching to open the base; filling the trench with a polymer filling; and chemical-mechanical polishing the substrate. Preferred Features: The pad nitride is silicon nitride. The trench filling is amorphous silicon, silicon-germanium or germanium.