公开(公告)号：WO0197284A3

公开(公告)日：2002-04-25

申请号：PCT/US0119001

申请日：2001-06-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： AMRACOST MICHAEL ,  SPULER BRUNO ,  BRASE GABRIELA ,  GUTMANN ALOIS

IPC: H01L21/768

CPC classification number: H01L21/76808

Abstract: A method is provided for forming a step in a layer of material (16). The method includes forming the layer over a substrate. A cavity (24) is formed in a portion of an upper surface of the layer. The formed cavity is filled with a filler material (26) to provide a substantially planar surface over the substrate. A photoresist layer is formed over the substantially planar surface over the substrate. An aperture (30) is formed in the photoresist layer in registration with the formed cavity. The aperture exposes a portion of the filler material. The exposed portion (32) of the filler material is removed along with a contiguous portion of the layer (16) to form the step in the indentation. The cavity may be either a trench or a via. A 'Trench First' approach and a 'Via First' approach are described.

Abstract translation: 提供了一种用于在材料层中形成台阶的方法。 该方法包括在衬底上形成该层。 在该层的上表面的一部分中形成空腔。 形成的空腔填充有填充材料，以在衬底上提供基本平坦的表面。 光致抗蚀剂层形成在衬底上的基本平坦的表面上。 光致抗蚀剂层中形成有与形成的空腔对准的孔。 孔径暴露了填充材料的一部分。 填充材料的暴露部分与层的连续部分一起被去除以形成凹陷中的台阶。 空腔可以是沟槽或通孔。 描述了“首先采取沟通”方式和“首选”方式。

公开(公告)号：WO0203457A2

公开(公告)日：2002-01-10

申请号：PCT/US0121161

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： BRASE GABRIELA ,  SCHROEDER UWE PAUL ,  HOLLOWAY KAREN LYNNE

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnection pattern is formed over the surface of a silicon wafer in which both the vias and the trenches of the pattern are filled with copper. The process of filling the vias and trenches involves use of a silicon nitride film as an etch stop and the filling of the vias with an anti-reflection coating.

Abstract translation: 在硅晶片的表面上形成互连图案，其中图案的通孔和沟槽均填充有铜。 填充通孔和沟槽的过程涉及使用氮化硅膜作为蚀刻停止件并且用防反射涂层填充通孔。

公开(公告)号：WO0201632A3

公开(公告)日：2003-10-23

申请号：PCT/US0120354

申请日：2001-06-27

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： MATUSIEWICZ GERALD ,  BRASE GABRIELA

IPC: H01L23/12 ,  H01L23/528 ,  H01L23/522 ,  H01L23/31

CPC classification number: H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Damage to interconnect structures including vias and/or device interconnects through insulators having a low modulus of elasticity between materials having different coefficients of thermal expansion (CTEs) by providing bends or jogs in an interconnect which limit the axial length of the interconnect adjacent the via or device contact in accordance with the difference in CTEs. The interconnect thus limits the development of shear forces and serves to relieve them by flexure of the interconnect across portions of the narrow width of the interconnect; preventing concentration of shear forces near the via or device contact. Implementation as a design rule based on limitation of length of a straight segment of an interconnect trace is preferred.

Abstract translation: 通过在互连中提供弯曲或点动来限制邻近通孔的互连的轴向长度，从而损坏互连结构，包括通孔和/或器件互连通过具有不同热膨胀系数（CTE）的材料之间具有低弹性模量的绝缘体，或 设备接触符合CTE的不同。 因此，互连限制了剪切力的发展，并且用于通过互连件在互连的窄宽度的部分上的挠曲来缓解它们; 防止通孔或器件接触附近的剪切力集中。 作为基于互连迹线的直线段的长度的限制的设计规则的实现是优选的。