公开(公告)号：JP2000235786A

公开(公告)日：2000-08-29

申请号：JP2000035922

申请日：2000-02-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  GERD FRANKOVSKI

IPC: G11C7/00 ,  G11C7/10 ,  G11C19/00 ,  G11C19/28 ,  H03K17/22 ,  H03K19/096

Abstract: PROBLEM TO BE SOLVED: To obtain a low voltage bus signalling architecture by providing a storage circuit which stores data after it is placed in a set state, an output circuit which connects stored data to an output by responding to an output strobe pulse and a reset circuit resetting the storage circuit by responding to the falling edge of the output strobe pulse. SOLUTION: This low voltage bus signalling architecture 20 has a driver 200 and a storage part 210. The driver 200 is an n-channel MOSFET inverter and inputs an input logic signal being on a line 203. The storage part 210 has a latch 250, an output circuit 260 and a reset circuit 270. The output circuit 260 connects stored data to an output DQ by responding to an output strobe pulse PNTo1. The reset circuit 270 precharges the storage part 210 via a first transistor 240 by responding to the falling edge of the pulse PNTo1.

公开(公告)号：JP2000315381A

公开(公告)日：2000-11-14

申请号：JP2000078940

申请日：2000-03-21

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： GERD FRANKOVSKI

IPC: G11C7/00 ,  G06F5/06 ,  G11C8/04

Abstract: PROBLEM TO BE SOLVED: To generate a pointer including a pointer with almost a same delay concerning a clock. SOLUTION: A pointer generating circuit supplies a clock cycle; a shift register has plural latches for storing data bits; a switch by which a 1st latch receives a flag bit at a 1st clock cycle of the clock and transfers the flag bit to a shift register at the 1st clock cycle connects the last latch to the 1st latch after the flag bit has been transferred to the shift register; the flag bit is transferred to the next latch, and when the next latch is the final one, this latch is made to be a 1st latch, and thus, a pointer signal is generated in each consecutive clock according to the data bit stored in the clock cycle and latch in each clock cycle.

公开(公告)号：JP2000338197A

公开(公告)日：2000-12-08

申请号：JP2000095079

申请日：2000-03-30

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： GERD FRANKOVSKI ,  TERLETZKI HARTMUD

IPC: G01R31/28 ,  G01R29/027 ,  G01R31/30 ,  G01R31/317 ,  G01R31/3193 ,  H01L21/66

Abstract: PROBLEM TO BE SOLVED: To execute a high resolution test by using an inexpensive tester of comparatively low frequency by mounting a plurality of delay elements capable of being enabled and disabled by pulses from an operation circuit, and the like. SOLUTION: A semiconductor circuit 12 is formed on a single crystalline such as silicon or a substrate 16 (that is, die or chip), and has a plurality of pins 181-18n. These pins 181-18n are connected to a tester 14 through lines 201-20n to be communicated with the tester 14. The tester 14 transmits a signal to the circuit 12, further receives the signal from the circuit 12 and processes the signal. The circuit 12 has an operation circuit 22 and a test circuit 24. The operation circuit 22 generates pulses of very short width. The test circuit 24 has a plurality of delay elements, and these delay elements are enabled and disabled by pulses from the operation circuit 22. By applying this device, the quality of high frequency of the signal of the circuit is measured by a low frequency test device.