公开(公告)号：JP2000228504A

公开(公告)日：2000-08-15

申请号：JP2000028340

申请日：2000-02-04

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  LAROSA GIUSEPPE ,  RADENS CARL ,  DIVAKARUNI RAMA ,  GRUENING ULRIKE

IPC: H01L21/76 ,  H01L21/763 ,  H01L21/765 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a dynamic random access memory formed at a semiconductor body comprising individual paired memory cell separated each other by a vertical electric isolation trench and separated from a support circuit. SOLUTION: An isolation trench 20, comprising a side wall, upper part, and lower part, encloses the region of a semiconductor body 10 comprising a memory cell. Thus, the paired memory cell is electrically separated each other, while separated from a support circuit which is not in the enclosed region but contained in the semiconductor body. The isolation trench lower-part is filled with a conductive material 14, which material comprises a side wall part which is at least partially separated from the trench lower-part side wall by a first electric insulator and a lower part electrically connecting to the semiconductor body. The isolation trench upper-part is filled with a second electric insulator.

公开(公告)号：WO0191179A3

公开(公告)日：2002-04-11

申请号：PCT/US0116140

申请日：2001-05-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ALSMEIER JOHANN ,  LAROSA GIUSEPPE ,  LUKAITIS JOSEPH ,  REAMGARAJAN RAJESH

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/76237

Abstract: Semiconductor device and method of manufacturing the same are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. After formation of the oxide liner, first regions of the semiconductor substrate are masked, leaving second regions thereof exposed. N-type devices are to be formed in the first regions and p-type devices are to be formed in the second regions. N-type ions may then be implanted into sidewalls of the trenches in the second regions. The mask is stripped and formation of the semiconductor device may be carried out in a conventional manner. The n-type ions are preferably only implanted into sidewalls where PMOSFETs are formed.

Abstract translation: 提供半导体装置及其制造方法。 在半导体衬底中形成沟槽。 优选在沟槽的表面上形成薄的氧化物衬垫。 在形成氧化物衬垫之后，掩模半导体衬底的第一区域，使第二区域暴露。 在第一区域中将形成N型器件，并且在第二区域中将形成p型器件。 然后可以将N型离子注入到第二区域中的沟槽的侧壁中。 剥离掩模，并且可以以常规方式进行半导体器件的形成。 n型离子优选仅被注入形成PMOSFET的侧壁。

公开(公告)号：WO0188977A3

公开(公告)日：2002-06-13

申请号：PCT/US0115759

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARARUNI RAMA ,  SRINIVASAN RADHIKA ,  HO HERBERT ,  BEINTNER JOACHEN ,  LI YUJUN ,  LAROSA GIUSEPPE

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/76224

Abstract: A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.

Abstract translation: 提供半导体器件及其制造方法。 在半导体衬底中形成沟槽。 优选在沟槽的表面上形成薄的氧化物衬垫。 氮化物衬垫形成在沟槽中。 电荷被困在氮化物衬垫中。 在优选实施例中，沟槽通过HDP工艺填充氧化物以增加在氮化物衬垫中捕获的电荷量。 优选地，氧化物填充物直接形成在氮化物衬垫上。

公开(公告)号：DE60134848D1

公开(公告)日：2008-08-28

申请号：DE60134848

申请日：2001-05-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ALSMEIER JOHANN ,  LAROSA GIUSEPPE ,  LUKAITIS JOSEPH ,  RENGARAJAN RAJESH

IPC: H01L21/762

Abstract: A semiconductor device and method of manufacturing the same are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. After formation of the oxide liner, first regions of the semiconductor substrate are masked, leaving second regions thereof exposed. N-type devices are to be formed in the first regions and p-type devices are to be formed in the second regions. N-type ions may then be implanted into sidewalls of the trenches in the second regions. The mask is stripped and formation of the semiconductor device may be carried out in a conventional manner. The n-type ions are preferably only implanted into sidewalls where PMOSFETs are formed.

公开(公告)号：JP2004213864A

公开(公告)日：2004-07-29

申请号：JP2003403813

申请日：2003-12-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LAROSA GIUSEPPE ,  STRONG ALVIN W

IPC: G01R31/28 ,  G11C11/401 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50 ,  H01L21/8242 ,  H01L27/108

CPC classification number: G11C29/50 ,  G11C11/401 ,  G11C2029/5002

Abstract: PROBLEM TO BE SOLVED: To provide particular performance data that are not generally obtained by a large-scale integrated testing method by evaluating the performance characteristic of each memory cell in particular about a random access memory cell.
SOLUTION: The present invention provides an on-chip circuit and a testing method which evaluate transistor electric charge transfer performance and electric charge storage capability of a DRAM cell in an real operating environment. The on-chip circuit and the testing method can evaluate deterioration of a cell transfer device by a MOSFET deterioration mechanism that becomes active at the time of electric charge transfer or storage in an operating state or burn-in state. The on-chip circuit forces and senses voltage in each DRAM storage capacitor, displays each storage capacitor charge leakage rate and enables a pulse testing method for calculating an electric charge transfer rate between a bit line of the DRAM cell and the storage capacitor.
COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：提供通常通过大规模集成测试方法获得的特定性能数据，通过评估每个存储器单元的性能特征，特别是关于随机存取存储单元。 解决方案：本发明提供一种在真实的操作环境中评估DRAM单元的晶体管电荷转移性能和电荷存储能力的片上电路和测试方法。 片上电路和测试方法可以通过在电荷转移或存储在操作状态或老化状态时变为活动的MOSFET劣化机制来评估电池转移装置的劣化。 片上电路强制并感测每个DRAM存储电容器中的电压，显示每个存储电容器的电荷泄漏率，并且能够实现用于计算DRAM单元的位线和存储电容器之间的电荷传输速率的脉冲测试方法。 版权所有（C）2004，JPO＆NCIPI