公开(公告)号：WO0142996A3

公开(公告)日：2002-02-14

申请号：PCT/US0033146

申请日：2000-12-06

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANSFIELD SCOTT M ,  LIEBMANN LARS W ,  BUTT SHAHID ,  HAFFNER HENNING

IPC: G03F1/00 ,  G03F1/36 ,  G03F7/20 ,  G06F17/50

CPC classification number: G03F1/36 ,  G03F7/70441

Abstract: A semiconductor device can be fabricated using a photomask that has been modified using an assist feature design method based on normalized feature spacing. Before the device can be fabricated, a layout of original shapes is designed (402). For at least some of the original shapes, the width of the shape and a distance to at least one neighboring shape are measured (404). A modified shape can then be generated by moving edges of the original shape based on the width and distance measurements (406). This modification can be performed on some or all of the original shapes (408). For each of the modified shapes, a normalized space and correct number of assist features can be computed (410). The layout is then modified by adding the correct number of assist features in a space between the modified shape and the neighboring shape (412). This modified layout can then be used in producing a photomask, which can in turn be used to produce a semiconductor device.

Abstract translation: 可以使用已经使用基于归一化特征间隔的辅助特征设计方法修改的光掩模来制造半导体器件。 在可以制造设备之前，设计原始形状的布局（402）。 对于至少一些原始形状，测量形状的宽度和至少一个相邻形状的距离（404）。 然后可以通过基于宽度和距离测量来移动原始形状的边缘来生成修改的形状（406）。 可以对部分或全部原始形状执行该修改（408）。 对于每个修改的形状，可以计算归一化空间和正确数量的辅助特征（410）。 然后通过在修改的形状和相邻形状之间的空间中添加正确数量的辅助特征来修改布局（412）。 然后，该修改后的布局可用于制造光掩模，光掩模又可用于制造半导体器件。

公开(公告)号：EP1952289A4

公开(公告)日：2009-07-29

申请号：EP06816698

申请日：2006-10-11

Applicant: IBM

Inventor： MANSFIELD SCOTT M ,  LIEBMANN LARS W ,  GRAUR IOANA ,  KRASNOPEROVA AZALIA

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.

公开(公告)号：WO2008022178A3

公开(公告)日：2008-10-16

申请号：PCT/US2007075977

申请日：2007-08-15

Applicant: IBM ,  HAN GENG ,  MANSFIELD SCOTT M

Inventor： HAN GENG ,  MANSFIELD SCOTT M

IPC: G03C5/00 ,  G03F9/00

CPC classification number: G03F7/70441 ,  G03F7/705

Abstract: A methodology to improve the through-process model calibration accuracy of a semiconductor manufacturing process using lithographic methods by setting the correct defocus and image plane position in a patterning process model build. Separations of the optical model and the photoresist model are employed by separating out the adverse effects of the exposure tool from the effects of the photoresist. The exposure tool is adjusted to compensate for the errors. The methodology includes a determination of where the simulator best focus location is in comparison to the empirically derived best focus location.

Abstract translation: 通过在图案化工艺模型构建中设置正确的离焦和图像平面位置，使用光刻方法来提高半导体制造工艺的贯穿工艺模型校准精度的方法。 通过从光刻胶的作用中分离曝光工具的不利影响来采用光学模型和光刻胶模型的分离。 调整曝光工具以补偿错误。 该方法包括确定模拟器最佳聚焦位置与经验导出的最佳聚焦位置相比较的位置。

公开(公告)号：WO2008055195A3

公开(公告)日：2008-08-07

申请号：PCT/US2007083145

申请日：2007-10-31

Applicant: IBM ,  MANSFIELD SCOTT M ,  LIEBMANN LARS W ,  GRAUR IOANA ,  HAN GENG

Inventor： MANSFIELD SCOTT M ,  LIEBMANN LARS W ,  GRAUR IOANA ,  HAN GENG

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A method of designing an integrated circuit is provided in which the design layout is optimized using a process model (54) until the design constraints (11) are satisfied by the image contours (51) simulated by the process model (54). The process model (54) used in the design phase need not be as accurate as the lithographic model (61) used in preparing the lithographic mask layout during data prep. The resulting image contours (51) are then included with the modified, optimized design layout to the data prep process (60), in which the mask layout is optimized using the lithographic process model (61), for example, including RET and OPC. The mask layout optimization (60) matches the images simulated by the lithographic process model (61) with the image contours (51) generated during the design phase, which ensures that the design and manufacturability constraints specified by the designer are satisfied by the optimized mask layout (60).

Abstract translation: 提供一种设计集成电路的方法，其中使用过程模型（54）优化设计布局，直到由过程模型（54）模拟的图像轮廓（51）满足设计约束（11）。 在设计阶段使用的过程模型（54）不需要与在数据准备期间制备光刻掩模布局时使用的光刻模型（61）一样精确。 然后将所得图像轮廓（51）与经修改的优化设计布局一起包括到数据准备过程（60）中，其中使用例如包括RET和OPC的光刻过程模型（61）来优化掩模布局。 掩模版图优化（60）将由光刻工艺模型（61）模拟的图像与在设计阶段期间生成的图像轮廓（51）相匹配，这确保由设计者指定的设计和可制造性约束通过优化掩模 布局（60）。