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    SELF ALIGNED TRENCH AND METHOD OF FORMING THE SAME
    1.
    发明申请
    SELF ALIGNED TRENCH AND METHOD OF FORMING THE SAME 审中-公开
    自对准TRENCH及其形成方法

    公开(公告)号：WO0225730A8

    公开(公告)日：2002-12-27

    申请号：PCT/US0142263

    申请日：2001-09-24

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： KUNKEL GERHARD ,  BUTT SHAHID ,  DIVAKARUNI RAMACHANDRAN ,  REITH ARMIN M ,  NAEEM MUNIR D

    IPC: H01L21/8242

    CPC classification number: H01L27/10864 ,  H01L27/1087 ,  H01L27/10891

    Abstract: A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) (104) is formed over a semiconductor region (e.g., a silicon substrate) (100). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) (112, 120) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench (122) can be etched in the semiconductor region. The trench would be substantially aligned to the second material.

    Abstract translation: 形成沟槽的方法可用于制造动态随机存取存储器（DRAM）单元。 在一个方面，在半导体区域（例如，硅衬底）（100）上形成第一材料（例如，多晶硅）（104）的第一层。 图案化第一层以去除第一材料的部分。 然后可以沉积第二材料（例如氧化物）（112,120）以填充去除第一材料的部分。 在去除第一材料的第一层的剩余部分之后，可以在半导体区域中蚀刻沟槽（122）。 沟槽将基本上对准第二材料。

    SELF ALIGNED TRENCH AND METHOD OF FORMING THE SAME
    2.
    发明申请
    SELF ALIGNED TRENCH AND METHOD OF FORMING THE SAME 审中-公开
    自定义沟槽和形成它的方法

    公开(公告)号：WO0225730A3

    公开(公告)日：2002-10-24

    申请号：PCT/US0142263

    申请日：2001-09-24

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： KUNKEL GERHARD ,  BUTT SHAHID ,  DIVAKARUNI RAMACHANDRAN ,  REITH ARMIN M ,  NAEEM MUNIR D

    IPC: H01L21/8242

    CPC classification number: H01L27/10864 ,  H01L27/1087 ,  H01L27/10891

    Abstract: A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) (104) is formed over a semiconductor region (e.g., a silicon substrate) (100). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) (112, 120) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench (122) can be etched in the semiconductor region. The trench would be substantially aligned to the second material.

    Abstract translation: 可以在制造动态随机存取存储器（DRAM）单元中使用形成沟槽的方法。 在一个方面，第一材料（例如，多晶硅）（104）的第一层形成在半导体区域（例如，硅衬底）（100）之上。 第一层被图案化以去除第一材料的一部分。 然后可以沉积第二材料（例如氧化物）（112,120）以填充第一材料被去除的部分。 在去除第一层第一材料的剩余部分之后，可以在半导体区中蚀刻沟槽（122）。 沟槽将基本上与第二材料对齐。

    DESIGN OF PHOTOMASKS FOR SEMICONDUCTOR DEVICE FABRICATION
    3.
    发明申请
    DESIGN OF PHOTOMASKS FOR SEMICONDUCTOR DEVICE FABRICATION 审中-公开
    用于半导体器件制造的光电子设计

    公开(公告)号：WO0142996A3

    公开(公告)日：2002-02-14

    申请号：PCT/US0033146

    申请日：2000-12-06

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： MANSFIELD SCOTT M ,  LIEBMANN LARS W ,  BUTT SHAHID ,  HAFFNER HENNING

    IPC: G03F1/00 ,  G03F1/36 ,  G03F7/20 ,  G06F17/50

    CPC classification number: G03F1/36 ,  G03F7/70441

    Abstract: A semiconductor device can be fabricated using a photomask that has been modified using an assist feature design method based on normalized feature spacing. Before the device can be fabricated, a layout of original shapes is designed (402). For at least some of the original shapes, the width of the shape and a distance to at least one neighboring shape are measured (404). A modified shape can then be generated by moving edges of the original shape based on the width and distance measurements (406). This modification can be performed on some or all of the original shapes (408). For each of the modified shapes, a normalized space and correct number of assist features can be computed (410). The layout is then modified by adding the correct number of assist features in a space between the modified shape and the neighboring shape (412). This modified layout can then be used in producing a photomask, which can in turn be used to produce a semiconductor device.

    Abstract translation: 可以使用已经使用基于归一化特征间隔的辅助特征设计方法修改的光掩模来制造半导体器件。 在可以制造设备之前，设计原始形状的布局（402）。 对于至少一些原始形状，测量形状的宽度和至少一个相邻形状的距离（404）。 然后可以通过基于宽度和距离测量来移动原始形状的边缘来生成修改的形状（406）。 可以对部分或全部原始形状执行该修改（408）。 对于每个修改的形状，可以计算归一化空间和正确数量的辅助特征（410）。 然后通过在修改的形状和相邻形状之间的空间中添加正确数量的辅助特征来修改布局（412）。 然后，该修改后的布局可用于制造光掩模，光掩模又可用于制造半导体器件。

    METHOD FOR ETCHING
    4.
    发明专利
    METHOD FOR ETCHING 失效

    公开(公告)号：JP2000315684A

    公开(公告)日：2000-11-14

    申请号：JP2000111181

    申请日：2000-04-12

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： BUTT SHAHID ,  SCHROEDER UWE PAUL

    IPC: H01L21/302 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/311

    Abstract: PROBLEM TO BE SOLVED: To provide a method for transferring an image to a surface by using a substrate layer in a front layer imaging lithography. SOLUTION: This method for etching comprises the steps of forming a substrate layer 14 on a surface and a front layer 16 on the layer 14, patterning the front layer to partly expose the substrate layer, forming a layer containing silicon on the exposed portion of the substrate layer, removing the front layer, exposing the substrate layer except a portion which is covered with the silicon layer, and etching the substrate layer except a portion having the silicon layer, thereby causing the surface to be expose.

    PROJECTING PART IMPROVING MASK FOR IMPROVING PROCESS WINDOW
    5.
    发明专利
    PROJECTING PART IMPROVING MASK FOR IMPROVING PROCESS WINDOW 失效

    公开(公告)号：JP2000284466A

    公开(公告)日：2000-10-13

    申请号：JP2000069197

    申请日：2000-03-13

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： CARPI ENIO ,  BUTT SHAHID

    IPC: G03F1/00 ,  H01L21/027 ,  G03F1/08

    Abstract: PROBLEM TO BE SOLVED: To provide a mask pattern capable of increasing the depth of focus and exposure latitude while maintaining or improving the resolution for the characteristics desired to be imaged. SOLUTION: The surface of a substrate 18 is provided with plural elongated structures 13 which are arranged nearly parallel to each other and plural projecting parts 14 below the resolution which extend transversely into the spaces between these elongated structures from the elongated structures. The plural projecting parts 14 have nearly the same sizes in the direction parallel to the elongated structures 13. The plural projecting parts 14 are periodically arranged apart spaced intervals in the direction parallel to the elongated structures 13. The elongated structures 13 and the projecting parts 14 are formed of energy absorption materials containing at least one among chromium, carbon and molybdenum.

    DYNAMIC RANDOM ACCESS MEMORY
    6.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY 审中-公开
    动态随机访问存储器

    公开(公告)号：WO0201568A3

    公开(公告)日：2002-06-06

    申请号：PCT/US0120406

    申请日：2001-06-26

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： KUNKEL GERHARD ,  BUTT SHAHID

    IPC: G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/409

    CPC classification number: H01L27/10882 ,  G11C11/4097 ,  H01L27/10841

    Abstract: A dynamic random access memory is formed in a silicon chip in arrays of clusters, each of four cells in a single active area. Each active area is cross-shaped with vertical trenches at the four ends of the two crossbars. The central region of the active area where the two crossbars intersect serves as the common base region of the four transistors of the cluster. The top of the base region serves as a common drain for the four transistors and each transistor has a separate channel along the wall of its associated vertical trench that provides its storage capacitor. Each cluster includes a common bit line and four separate word-line contacts.

    Abstract translation: 动态随机存取存储器形成在簇的阵列中的硅芯片中，四个单元中的每一个在单个有效区域中。 每个活动区域在两根横杆的四端带有垂直沟槽的十字形。 两个横杆相交的有效区域的中心区域用作该群集的四个晶体管的公共基极区域。 基极区域的顶部用作四个晶体管的公共漏极，并且每个晶体管沿着其提供其存储电容器的相关垂直沟槽的壁具有单独的沟道。 每个群集包括一个公共位线和四个单独的字线接触。

    SEMICONDUCTOR DEVICE FABRICATION USING A PHOTOMASK DESIGNED USING MODELING AND EMPIRICAL TESTING
    7.
    发明申请
    SEMICONDUCTOR DEVICE FABRICATION USING A PHOTOMASK DESIGNED USING MODELING AND EMPIRICAL TESTING 审中-公开
    使用建模和实验测试设计的光电子半导体器件制造

    公开(公告)号：WO0184237A3

    公开(公告)日：2002-06-27

    申请号：PCT/US0111318

    申请日：2001-04-06

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： BUTT SHAHID ,  HAFFNER HENNING ,  FRANKOWSKY BEATE

    IPC: G03F1/00 ,  G03F1/14

    CPC classification number: G03F1/68 ,  G03F1/36 ,  G03F1/44 ,  Y10S977/839 ,  Y10S977/887

    Abstract: A method of fabricating a semiconductor device is outlined in Figure 3. An ideal (or desired) pattern of a layer of the semiconductor device is designed (305). A first pass corrected pattern is then derived by correcting the ideal patterns for major effects, e.g., aerial image effects (315, 320). A second pass corrected pattern is then derived by correcting the first pass corrected patterns for remaining errors (340). The second pass corrected pattern can be used to build a photomask (345). The photomask can then be used to produce a semiconductor device, such a memory chip or logic chip (350).

    Abstract translation: 制造半导体器件的方法在图3中概述。设计半导体器件层的理想（或期望的）图案（305）。 然后通过校正主要效果（例如，空中影像效果）的理想图案（315,320）来导出第一通过校正图案。 然后通过校正用于剩余错误的第一通过校正图案来导出第二遍校正图案（340）。 第二遍校正图案可用于构建光掩模（345）。 然后可以使用光掩模来制造半导体器件，诸如存储芯片或逻辑芯片（350）。

    8.
    发明专利
    未知

    公开(公告)号：DE60106256D1

    公开(公告)日：2004-11-11

    申请号：DE60106256

    申请日：2001-06-26

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： KUNKEL GERHARD ,  BUTT SHAHID ,  RADENS CARL J

    IPC: G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/00

    Abstract: A dynamic random access memory is formed in a silicon chip in arrays of clusters, each of four cells in a single active area. Each active area is cross-shaped with vertical trenches at the four ends of the two crossbars. The central region of the active area where the two crossbars intersect serves as the common base region of the four transistors of the cluster. The top of the base region serves as a common drain for the four transistors and each transistor has a separate channel along the wall of its associated vertical trench that provides its storage capacitor. Each cluster includes a common bit line and four separate word-line contacts.

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