公开(公告)号：WO0199181A2

公开(公告)日：2001-12-27

申请号：PCT/US0119241

申请日：2001-06-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： RAMACHANDRAN RAVIKUMAR ,  NAGEL NICOLAS ,  PARKS CHRISTOPHER

IPC: H01L21/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L21/76849 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76861 ,  H01L21/7687 ,  H01L27/10855

Abstract: A method for cleaning an oxidized diffusion barrier layer, in accordance with the present invention, includes providing a conductive diffusion barrier layer (26) employed for preventing oxygen and metal diffusion therethrough and providing a wet chemical etchant (wet etch) including hydrofluoric acid. The diffusion barrier layer (26) is etched with the wet chemical etchant to remove oxides from the diffusion barrier layer such that by employing the wet chemical etchant linear electrical behavior is achieved through the diffusion barrier layer.

Abstract translation: 根据本发明的用于清洁氧化的扩散阻挡层的方法包括提供用于防止氧和金属扩散的导电扩散阻挡层（26），并提供包括氢氟酸的湿化学蚀刻剂（湿蚀刻）。 用湿化学蚀刻剂蚀刻扩散阻挡层（26），以从扩散阻挡层去除氧化物，使得通过使用湿式化学蚀刻剂，通过扩散阻挡层实现线性电性能。

公开(公告)号：JP2000001778A

公开(公告)日：2000-01-07

申请号：JP10654899

申请日：1999-04-14

Applicant: IBM ,  TOSHIBA CORP

Inventor： BILARGE SADESAI ,  KATADA TOMIO ,  PARKS CHRISTOPHER ,  JOHN BENEDICT

IPC: C23C14/35 ,  H01L21/285

Abstract: PROBLEM TO BE SOLVED: To provide a method for producing a laminated thin film capable of precisely controlling the film thickness or the compsn. SOLUTION: A uniform compd. target 21 composed of >= two materials is used, the magnetic field is periodically changed, and the depositing rate of one material is periodically increased to that of the other material. The change of the magnetic field changes the magnetic field sweep time and changes the thickness of the deposition layer. In this case, the layer thickness is inversely proportioned to the magnetic field sweep time. Or, the magnetic intensity is changed to change the relative compsn. of sputter seed. In an electromagnet, it is executed by controlling the amplitude of the waveform of the input current, i.e., the maximum current.

公开(公告)号：JPH11135454A

公开(公告)日：1999-05-21

申请号：JP23405098

申请日：1998-08-20

Applicant: IBM ,  SIEMENS AG

Inventor： AJMERA ATUL C ,  DEHM CHRISTINE ,  DOMENICUCCI ANTHONY G ,  GIFFORD GEORGE G ,  LOH STEPHEN K ,  PARKS CHRISTOPHER ,  SARDESAI VIRAJI Y

IPC: H01L21/28 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To provide an improved method for forming a metallic silicide conductor in an integrated circuit. SOLUTION: A porous barrier is formed to prevent the thermal movement of silicon by enriching the grain boundary of a polysilicon layer 25 with nitrogen without forming an individual barrier layer. A reduction in the movement of the silicon prevents the agglomeration of the silicon in a metallic silicide layer formed on a policide gate/interconnection structure. The aggromelation of the silicon is a precedent advance phenomenon of a polycide inversion and hence effectively eliminates the polycide inversion passing through a lower oxide and damaging a device.

公开(公告)号：JPH1074910A

公开(公告)日：1998-03-17

申请号：JP19424797

申请日：1997-07-18

Applicant: IBM ,  SIEMENS AG

Inventor： ALSMEIER JOHANN ,  MANDELMAN JACK ALLAN ,  O'NEILL JAMES ANTHONY ,  PARKS CHRISTOPHER ,  PARRIES PAUL CHRISTIAN

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain an integrated circuit capacitor of high capacitance by using an inversion layer inside a lightly doped substrate as a plate paired electrode for a capacitor. SOLUTION: A depletion region 302 is formed around a memory node 224 peripheral besides neighboring to an N-separation band 204 by forming an inversion node capacitor 200 on a P-substrate 202. An inversion region 304 is formed inside the depletion region 302 near the memory node 224. The inversion region is connected to the N-separation band 204. Accordingly, an electric field between the memory node 224 and the paired electrode of the inversion region 304 is partially defined by a work function difference between the N- separation band 204 and an N material inside the memory node 224. The N separation band 204 functions as a wiring connection to a common pared electrode of the inversion region 304 of the capacitor 200. Thereby, conductivity of the N separation band 204 plays a more important role than the designing of prior arts.

公开(公告)号：DE69836117T2

公开(公告)日：2007-04-19

申请号：DE69836117

申请日：1998-07-28

Applicant: SIEMENS AG ,  IBM

Inventor： AJMERA ATUL C ,  DEHM CHRISTINE ,  DOMENICUCCI ANTHONY G ,  GIFFORD GEORGE G ,  LOH STEPHEN K ,  PARKS CHRISTOPHER ,  SARDESAI VIRAJI Y

IPC: H01L21/28 ,  H01L29/49

Abstract: A "porous barrier" is formed without formation of a discrete barrier layer by enriching grain boundaries of a body of polysilicon with nitrogen to inhibit thermal mobility of silicon species therealong. In a polycide gate/interconnect structure, the reduced mobility of silicon suppresses agglomeration of silicon in a metal silicide layer formed thereon. Since silicon agglomeration is a precursor of a polycide inversion phenomenon, polycide inversion which can pierce an underlying oxide and cause device failure is effectively avoided. The increased thermal stability of polycide structures and other structures including a body of polysilicon thus increases the heat budget that can be withstood by the structure and increases the manufacturing process window imposed by the presence of polysilicon which can be exploited in other processes such as annealing to develop a low resistance phase of refractory metal silicide included in the polycide structure, drive-in annealing for formation of source/drain regions of field effect transistors and the like.

公开(公告)号：DE69836117D1

公开(公告)日：2006-11-23

申请号：DE69836117

申请日：1998-07-28

Applicant: SIEMENS AG ,  IBM

Inventor： AJMERA ATUL C ,  DEHM CHRISTINE ,  DOMENICUCCI ANTHONY G ,  GIFFORD GEORGE G ,  LOH STEPHEN K ,  PARKS CHRISTOPHER ,  SARDESAI VIRAJI Y

IPC: H01L21/28 ,  H01L29/49

Abstract: A "porous barrier" is formed without formation of a discrete barrier layer by enriching grain boundaries of a body of polysilicon with nitrogen to inhibit thermal mobility of silicon species therealong. In a polycide gate/interconnect structure, the reduced mobility of silicon suppresses agglomeration of silicon in a metal silicide layer formed thereon. Since silicon agglomeration is a precursor of a polycide inversion phenomenon, polycide inversion which can pierce an underlying oxide and cause device failure is effectively avoided. The increased thermal stability of polycide structures and other structures including a body of polysilicon thus increases the heat budget that can be withstood by the structure and increases the manufacturing process window imposed by the presence of polysilicon which can be exploited in other processes such as annealing to develop a low resistance phase of refractory metal silicide included in the polycide structure, drive-in annealing for formation of source/drain regions of field effect transistors and the like.

公开(公告)号：DE102004013928A1

公开(公告)日：2004-10-28

申请号：DE102004013928

申请日：2004-03-22

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BELYANSKY MICHAEL ,  GLUSCHENKOV OLEG ,  KNORR ANDREAS ,  PARKS CHRISTOPHER

IPC: H01L21/762 ,  H01L21/316 ,  H01L21/3105 ,  H01L21/8242

Abstract: A trench isolation structure is formed in a substrate. One or more openings are formed in a surface of the substrate, and a liner layer is deposited at least along a bottom and sidewalls of the openings. A layer of doped oxide material is deposited at least in the openings, and the substrate is annealed to reflow the layer of doped oxide material. Only a portion near the surface of the substrate is removed from the layer of doped oxide material in the opening. A cap layer is deposited atop a remaining portion of the layer of doped oxide material in the opening.