公开(公告)号：US20220308288A1

公开(公告)日：2022-09-29

申请号：US17294645

申请日：2021-03-18

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Bo Tang ,  Yan Yang ,  Peng Zhang ,  Zhihua Li ,  Ruonan Liu ,  Fujun Sun ,  Kai Huang ,  Bin Li ,  Ling Xie ,  Wenwu Wang

IPC: G02B6/132 ,  H01L21/02 ,  H01L21/768 ,  H01L23/48 ,  H01L25/16 ,  H01L27/12 ,  G02B6/30

Abstract: A method for packaging a semiconductor structure, a packaging structure, and a chip. The method includes: forming the semiconductor structure on a SOI chip, where the semiconductor structure includes an edge coupler or a cavity structure; forming, through PECVD, silicon oxide on a surface of the semiconductor structure, where the surface is provided with an opening of a trench; and performing subsequent packaging. A characteristic of low step coverage of the PECVD is utilized for sealing an opening of a trench of the semiconductor structure, and addressed is an issue of a device failure due to the trench blocked by a packaging material in subsequent packaging.

公开(公告)号：US20160020274A1

公开(公告)日：2016-01-21

申请号：US14396709

申请日：2014-08-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jing Xu ,  Jiang Yan ,  Bangming Chen ,  Hongli Wang ,  Bo Tang ,  Zhaoyun Tang ,  Yefeng Xu ,  Chunlong Li ,  Mengmeng Yang

IPC: H01L29/06 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78654 ,  H01L29/78687 ,  H01L29/78696

Abstract: A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.

Abstract translation: 一种半导体器件，包括：具有第一半导体材料的衬底; 在所述基板上的第二半导体层; 第二半导体层上的第三半导体层，并且是器件形成区域; 在第三半导体层的两侧和基板上的隔离结构; 以及在第三半导体层的源极和漏极区域之下以及隔离结构和第二半导体层的端部之间的绝缘层。

公开(公告)号：US09306003B2

公开(公告)日：2016-04-05

申请号：US14396709

申请日：2014-08-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jing Xu ,  Jiang Yan ,  Bangming Chen ,  Hongli Wang ,  Bo Tang ,  Zhaoyun Tang ,  Yefeng Xu ,  Chunlong Li ,  Mengmeng Yang

IPC: H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/0653 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78654 ,  H01L29/78687 ,  H01L29/78696

Abstract: A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.

Abstract translation: 一种半导体器件，包括：具有第一半导体材料的衬底; 在所述基板上的第二半导体层; 第二半导体层上的第三半导体层，并且是器件形成区域; 在第三半导体层的两侧和基板上的隔离结构; 以及在第三半导体层的源极和漏极区域之下以及隔离结构和第二半导体层的端部之间的绝缘层。

公开(公告)号：US20160293695A1

公开(公告)日：2016-10-06

申请号：US14391889

申请日：2014-08-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jing Xu ,  Jiang Yan ,  Bangming Chen ,  Hongli Wang ,  Bo Tang ,  Zhaoyun Tang ,  Yefeng Xu ,  Chunlong Li ,  Mengmeng Yang

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L21/762 ,  H01L21/306 ,  H01L29/161 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/30604 ,  H01L21/762 ,  H01L21/764 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66568 ,  H01L29/78

Abstract: The present disclosure provides a semiconductor device, comprising: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an hollow cavity below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer. Such a device structure of the present disclosure incorporate the respective advantages of the bulk silicon device and the SOI device, and has characteristics of lower cost, smaller leakage current, lower power consumption, fast speed, simple process and high integration level. Meanwhile, the floating body effect and the spontaneous heating effect are eliminated as compared with the SOI device. Furthermore, the lower dielectric constant in the hollow cavity results in that it may withstand a higher voltage.

Abstract translation: 本公开提供一种半导体器件，包括：具有第一半导体材料的衬底; 在所述基板上的第二半导体层; 第二半导体层上的第三半导体层，并且是器件形成区域; 在第三半导体层的两侧和基板上的隔离结构; 以及在第三半导体层的源极和漏极区之下以及隔离结构和第二半导体层的端部之间的中空腔。 本公开的这种器件结构体现了本体硅器件和SOI器件的各自优点，具有成本更低，漏电流更小，功耗更低，速度快，工艺简单，集成度高的特点。 同时，与SOI器件相比，浮体效应和自发加热效应被消除。 此外，中空腔中的较低介电常数导致其可承受更高的电压。