公开(公告)号：US20160020274A1

公开(公告)日：2016-01-21

申请号：US14396709

申请日：2014-08-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jing Xu ,  Jiang Yan ,  Bangming Chen ,  Hongli Wang ,  Bo Tang ,  Zhaoyun Tang ,  Yefeng Xu ,  Chunlong Li ,  Mengmeng Yang

IPC: H01L29/06 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78654 ,  H01L29/78687 ,  H01L29/78696

Abstract: A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.

Abstract translation: 一种半导体器件，包括：具有第一半导体材料的衬底; 在所述基板上的第二半导体层; 第二半导体层上的第三半导体层，并且是器件形成区域; 在第三半导体层的两侧和基板上的隔离结构; 以及在第三半导体层的源极和漏极区域之下以及隔离结构和第二半导体层的端部之间的绝缘层。

公开(公告)号：US10096691B2

公开(公告)日：2018-10-09

申请号：US14812490

申请日：2015-07-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qingzhu Zhang ,  Lichuan Zhao ,  Xiongkun Yang ,  Huaxiang Yin ,  Jiang Yan ,  Junfeng Li ,  Tao Yang ,  Jinbiao Liu

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/167 ,  H01L29/417 ,  H01L21/28

Abstract: A method for forming a metal silicide. The method comprises: providing a substrate having a fin, a gate formed on the fin, and spacers formed on opposite sides of the gate; depositing a Ti metal layer; siliconizing the Ti metal layer; and removing unreacted Ti metal layer. As the Ti atoms have relatively stable characteristics, diffusion happens mostly to Si atoms while the Ti atoms rarely diffuse during the thermal annealing. As a result, current leakage can be prevented in a depletion region and thus leakage current of the substrate can be reduced.

公开(公告)号：US09831089B2

公开(公告)日：2017-11-28

申请号：US14407210

申请日：2013-08-30

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Hong Yang ,  Wenwu Wang ,  Jiang Yan ,  Weichun Luo

IPC: H01L21/28 ,  H01L21/8238 ,  H01L21/321 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/28088 ,  H01L21/321 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for adjusting an effective work function of a metal gate. The method includes forming a metal gate arrangement comprising at least a metal work function layer, and performing plasma treatment on at least one layer in the metal gate arrangement. In this way, it is possible to adjust the effective work function of the metal gate in a relatively flexible way.

公开(公告)号：US09331172B2

公开(公告)日：2016-05-03

申请号：US14426690

申请日：2012-11-13

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Lingkuan Meng ,  Xiaobin He ,  Guanglu Chen ,  Chao Zhao

IPC: H01L29/66 ,  H01L21/3105 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/31055 ,  H01L21/31144 ,  H01L21/32139 ,  H01L29/51 ,  H01L29/66492 ,  H01L29/66621 ,  H01L29/66833

Abstract: A method for manufacturing a dummy gate structure. The method may include: forming a dummy gate oxide layer and a dummy gate material layer on a semiconductor substrate sequentially; forming an ONO structure on the dummy gate material layer; forming a top amorphous silicon layer on the ONO structure; forming a patterned photoresist layer on the top amorphous silicon layer; etching the top amorphous silicon layer with the patterned photoresist layer as a mask, the etching being stopped on the ONO structure; etching the ONO structure with the patterned photoresist layer and a remaining portion of the top amorphous silicon layer as a mask, the etching being stopped on the dummy gate material layer; removing the patterned photoresist layer; and etching the dummy gate material layer, the etching being stopped at the dummy gate oxide layer to form a dummy gate structure.

Abstract translation: 一种用于制造虚拟栅极结构的方法。 该方法可以包括：顺序地在半导体衬底上形成伪栅极氧化物层和虚拟栅极材料层; 在虚拟栅极材料层上形成ONO结构; 在ONO结构上形成顶部非晶硅层; 在顶部非晶硅层上形成图案化的光致抗蚀剂层; 用图案化的光致抗蚀剂层作为掩模蚀刻顶部非晶硅层，蚀刻停止在ONO结构上; 用图案化的光致抗蚀剂层和顶部非晶硅层的剩余部分作为掩模蚀刻ONO结构，蚀刻停止在虚拟栅极材料层上; 去除图案化的光致抗蚀剂层; 并且蚀刻伪栅极材料层，蚀刻停止在虚设栅极氧化层处以形成虚拟栅极结构。

公开(公告)号：US09111863B2

公开(公告)日：2015-08-18

申请号：US14119869

申请日：2012-12-12

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L29/513 ,  H01L29/66545

Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon, and trimming the hard mask layer so that the trimmed hard mask layer has a width less than or equal to 22 nm; and etching the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed hard mask layer, and removing the hard mask layer and the top-layer amorphous silicon.

Abstract translation: 提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层，并修剪硬掩模层，使得修整的硬掩模层具有小于或等于22nm的宽度; 并根据修整的硬掩模层蚀刻顶层非晶硅，ONO结构的硬掩模和底层非晶硅，以及去除硬掩模层和顶层非晶硅。

公开(公告)号：US09306003B2

公开(公告)日：2016-04-05

申请号：US14396709

申请日：2014-08-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jing Xu ,  Jiang Yan ,  Bangming Chen ,  Hongli Wang ,  Bo Tang ,  Zhaoyun Tang ,  Yefeng Xu ,  Chunlong Li ,  Mengmeng Yang

IPC: H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/0653 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78654 ,  H01L29/78687 ,  H01L29/78696

Abstract: A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.

Abstract translation: 一种半导体器件，包括：具有第一半导体材料的衬底; 在所述基板上的第二半导体层; 第二半导体层上的第三半导体层，并且是器件形成区域; 在第三半导体层的两侧和基板上的隔离结构; 以及在第三半导体层的源极和漏极区域之下以及隔离结构和第二半导体层的端部之间的绝缘层。

公开(公告)号：US20140273426A1

公开(公告)日：2014-09-18

申请号：US14119869

申请日：2012-12-12

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC: H01L29/51

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L29/513 ,  H01L29/66545

Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon, and trimming the hard mask layer so that the trimmed hard mask layer has a width less than or equal to 22 nm; and etching the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed hard mask layer, and removing the hard mask layer and the top-layer amorphous silicon.

Abstract translation: 提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层，并修剪硬掩模层，使得修整的硬掩模层具有小于或等于22nm的宽度; 并根据修整的硬掩模层蚀刻顶层非晶硅，ONO结构的硬掩模和底层非晶硅，以及去除硬掩模层和顶层非晶硅。

公开(公告)号：US20160293695A1

公开(公告)日：2016-10-06

申请号：US14391889

申请日：2014-08-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jing Xu ,  Jiang Yan ,  Bangming Chen ,  Hongli Wang ,  Bo Tang ,  Zhaoyun Tang ,  Yefeng Xu ,  Chunlong Li ,  Mengmeng Yang

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L21/762 ,  H01L21/306 ,  H01L29/161 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/30604 ,  H01L21/762 ,  H01L21/764 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66568 ,  H01L29/78

Abstract: The present disclosure provides a semiconductor device, comprising: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an hollow cavity below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer. Such a device structure of the present disclosure incorporate the respective advantages of the bulk silicon device and the SOI device, and has characteristics of lower cost, smaller leakage current, lower power consumption, fast speed, simple process and high integration level. Meanwhile, the floating body effect and the spontaneous heating effect are eliminated as compared with the SOI device. Furthermore, the lower dielectric constant in the hollow cavity results in that it may withstand a higher voltage.

Abstract translation: 本公开提供一种半导体器件，包括：具有第一半导体材料的衬底; 在所述基板上的第二半导体层; 第二半导体层上的第三半导体层，并且是器件形成区域; 在第三半导体层的两侧和基板上的隔离结构; 以及在第三半导体层的源极和漏极区之下以及隔离结构和第二半导体层的端部之间的中空腔。 本公开的这种器件结构体现了本体硅器件和SOI器件的各自优点，具有成本更低，漏电流更小，功耗更低，速度快，工艺简单，集成度高的特点。 同时，与SOI器件相比，浮体效应和自发加热效应被消除。 此外，中空腔中的较低介电常数导致其可承受更高的电压。

公开(公告)号：US20150214332A1

公开(公告)日：2015-07-30

申请号：US14426690

申请日：2012-11-13

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Lingkuan Meng ,  Xiaobin He ,  Guanglu Chen ,  Chao Zhao

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/3105

CPC classification number: H01L29/66545 ,  H01L21/31055 ,  H01L21/31144 ,  H01L21/32139 ,  H01L29/51 ,  H01L29/66492 ,  H01L29/66621 ,  H01L29/66833

Abstract: A method for manufacturing a dummy gate structure. The method may include: forming a dummy gate oxide layer and a dummy gate material layer on a semiconductor substrate sequentially; forming an ONO structure on the dummy gate material layer; forming a top amorphous silicon layer on the ONO structure; forming a patterned photoresist layer on the top amorphous silicon layer; etching the top amorphous silicon layer with the patterned photoresist layer as a mask, the etching being stopped on the ONO structure; etching the ONO structure with the patterned photoresist layer and a remaining portion of the top amorphous silicon layer as a mask, the etching being stopped on the dummy gate material layer; removing the patterned photoresist layer; and etching the dummy gate material layer, the etching being stopped at the dummy gate oxide layer to form a dummy gate structure.

Abstract translation: 一种用于制造虚拟栅极结构的方法。 该方法可以包括：顺序地在半导体衬底上形成伪栅极氧化物层和虚拟栅极材料层; 在虚拟栅极材料层上形成ONO结构; 在ONO结构上形成顶部非晶硅层; 在顶部非晶硅层上形成图案化的光致抗蚀剂层; 用图案化的光致抗蚀剂层作为掩模蚀刻顶部非晶硅层，蚀刻停止在ONO结构上; 用图案化的光致抗蚀剂层和顶部非晶硅层的剩余部分作为掩模蚀刻ONO结构，蚀刻停止在虚拟栅极材料层上; 去除图案化的光致抗蚀剂层; 并且蚀刻伪栅极材料层，蚀刻停止在虚设栅极氧化层处以形成虚拟栅极结构。