公开(公告)号：US11930720B2

公开(公告)日：2024-03-12

申请号：US17495390

申请日：2021-10-06

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Meiyin Yang ,  Jun Luo ,  Yan Cui ,  Jing Xu

IPC: G11C11/16 ,  G11C11/18 ,  G11C11/22 ,  H10B61/00 ,  H10N52/00 ,  H10N52/80

CPC classification number: H10N52/80 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  G11C11/22 ,  H10B61/00 ,  H10N52/00 ,  G11C11/1659

Abstract: The present disclosure provides a storage unit, a data writing method and a data reading method thereof, a memory and an electronic device. The storage unit includes a semiconductor substrate, a first insulating medium layer, a ferroelectric thin film layer, a bottom electrode, a tunnel junction, a first metal interconnection portion, a second metal interconnection portion, a third metal interconnection portion and a fourth metal interconnection portion. The first insulating medium layer is formed on the semiconductor substrate, the ferroelectric thin film layer is disposed on the first insulating medium layer, the bottom electrode is formed on the ferroelectric thin film layer, and the tunnel junction is formed on the bottom electrode. The first metal interconnection portion is connected to a first end of the bottom electrode, and the third metal interconnection portion is connected to a second end of the bottom electrode. The second metal interconnection portion is connected to the ferroelectric thin film layer, and the fourth metal interconnection portion is connected to the tunnel junction. As compared with the prior art, the present disclosure can control a directional flipping of the magnetic moment in the tunnel junction based on the ferroelectric thin film layer provided. Based on the structural design of the storage unit, the present disclosure does not require an external magnetic field, and fully meets the requirement of high integration of the device.

公开(公告)号：US10991877B2

公开(公告)日：2021-04-27

申请号：US16560357

申请日：2019-09-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Meiyin Yang ,  Jun Luo ,  Sumei Wang ,  Jing Xu ,  Yanru Li ,  Junfeng Li ,  Yan Cui ,  Wenwu Wang ,  Tianchun Ye

IPC: H01L43/12 ,  H01F41/32 ,  H01F10/32 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  G11C11/56 ,  H01L27/22

Abstract: A multi-state memory and a method for manufacturing the same. A magnetoresistive tunnel junction is disposed on a spin-orbit coupling layer, and thermal annealing is performed after dopant ions are injected from a side of the magnetoresistive tunnel junction. The concentration of dopant ions in the magnetoresistive tunnel junction has a gradient variation along the direction that is perpendicular to the direction of the current and within the plane in which the spin-orbit coupling layer is located. Symmetry along the direction perpendicular to the direction of the current is broken. In a case a current flows into the spin-orbit coupling layer, resistance are outputted in multiple states in linearity with the current. The multi-state storage is achieved. It can meet a requirement on hardware of neural network synapses, and is applicable to calculation in a neural network.

公开(公告)号：US10756256B2

公开(公告)日：2020-08-25

申请号：US16411517

申请日：2019-05-14

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Meiyin Yang ,  Jun Luo ,  Tengzhi Yang ,  Jing Xu

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01F10/32 ,  H01F41/30 ,  G11C11/16 ,  H01L43/10

Abstract: A magnetoresistive random access memory and a method for manufacturing the same are provided, with which a stress layer covers a part of the protective layer along a direction of a current in the spin-orbit coupling layer, so that a stress is generated on the part of the magnetic layer locally due to the stress layer, thus a lateral asymmetric structure is formed in a direction perpendicular to the current source. In a case that a current is supplied to the spin-orbit coupling layer, the spin-orbit coupling effect in the magnetic layer is asymmetric due to the stress on the part of the magnetic layer, thereby realizing a deterministic switching of the magnetic moment under the function of the stress.

公开(公告)号：US20160293695A1

公开(公告)日：2016-10-06

申请号：US14391889

申请日：2014-08-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jing Xu ,  Jiang Yan ,  Bangming Chen ,  Hongli Wang ,  Bo Tang ,  Zhaoyun Tang ,  Yefeng Xu ,  Chunlong Li ,  Mengmeng Yang

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L21/762 ,  H01L21/306 ,  H01L29/161 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/30604 ,  H01L21/762 ,  H01L21/764 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66568 ,  H01L29/78

Abstract: The present disclosure provides a semiconductor device, comprising: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an hollow cavity below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer. Such a device structure of the present disclosure incorporate the respective advantages of the bulk silicon device and the SOI device, and has characteristics of lower cost, smaller leakage current, lower power consumption, fast speed, simple process and high integration level. Meanwhile, the floating body effect and the spontaneous heating effect are eliminated as compared with the SOI device. Furthermore, the lower dielectric constant in the hollow cavity results in that it may withstand a higher voltage.

Abstract translation: 本公开提供一种半导体器件，包括：具有第一半导体材料的衬底; 在所述基板上的第二半导体层; 第二半导体层上的第三半导体层，并且是器件形成区域; 在第三半导体层的两侧和基板上的隔离结构; 以及在第三半导体层的源极和漏极区之下以及隔离结构和第二半导体层的端部之间的中空腔。 本公开的这种器件结构体现了本体硅器件和SOI器件的各自优点，具有成本更低，漏电流更小，功耗更低，速度快，工艺简单，集成度高的特点。 同时，与SOI器件相比，浮体效应和自发加热效应被消除。 此外，中空腔中的较低介电常数导致其可承受更高的电压。

公开(公告)号：US12198746B2

公开(公告)日：2025-01-14

申请号：US17966476

申请日：2022-10-14

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yan Cui ,  Jun Luo ,  Meiyin Yang ,  Jing Xu

IPC: G11C11/16 ,  H03K19/20

Abstract: An in-memory computing circuit having reconfigurable logic, including: an input stage and N output stages which are cascaded. The input stage includes 2N STT-MTJs. Each output stage includes STT-MTJs, of which a quantity is equal to a half of a quantity of STT-MTJs in a just previous stage. Two STT-MTJs in the previous stage and one STT-MTJ in the subsequent stage form a double-input single-output in-memory computing unit. Each double-input single-output in-memory computing unit can implement the four logical operations, i.e., NAND, NOR, AND, and OR, under different configurations. Data storage and logical operations can be realized under the same circuit architecture, and reconfigurations among different logic can be achieved.

公开(公告)号：US20160020274A1

公开(公告)日：2016-01-21

申请号：US14396709

申请日：2014-08-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jing Xu ,  Jiang Yan ,  Bangming Chen ,  Hongli Wang ,  Bo Tang ,  Zhaoyun Tang ,  Yefeng Xu ,  Chunlong Li ,  Mengmeng Yang

IPC: H01L29/06 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78654 ,  H01L29/78687 ,  H01L29/78696

Abstract: A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.

Abstract translation: 一种半导体器件，包括：具有第一半导体材料的衬底; 在所述基板上的第二半导体层; 第二半导体层上的第三半导体层，并且是器件形成区域; 在第三半导体层的两侧和基板上的隔离结构; 以及在第三半导体层的源极和漏极区域之下以及隔离结构和第二半导体层的端部之间的绝缘层。

公开(公告)号：US20230178133A1

公开(公告)日：2023-06-08

申请号：US17966476

申请日：2022-10-14

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yan Cui ,  Jun Luo ,  Meiyin Yang ,  Jing Xu

IPC: G11C11/16 ,  H03K19/20

CPC classification number: G11C11/1697 ,  G11C11/1659 ,  H03K19/20

Abstract: An in-memory computing circuit having reconfigurable logic, including: an input stage and N output stages which are cascaded. The input stage includes 2N STT-MTJs. Each output stage includes STT-MTJs, of which a quantity is equal to a half of a quantity of STT-MTJs in a just previous stage. Two STT-MTJs in the previous stage and one STT-MTJ in the subsequent stage form a double-input single-output in-memory computing unit. Each double-input single-output in-memory computing unit can implement the four logical operations, i.e., NAND, NOR, AND, and OR, under different configurations. Data storage and logical operations can be realized under the same circuit architecture, and reconfigurations among different logic can be achieved.

公开(公告)号：US10700124B1

公开(公告)日：2020-06-30

申请号：US16411431

申请日：2019-05-14

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Meiyin Yang ,  Jun Luo ,  Tengzhi Yang ,  Jing Xu

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A spin-orbit torque magnetoresistive random access memory, and a method for manufacturing a spin-orbit torque magnetoresistive random access memory are provided. The spin-orbit torque magnetoresistive random access memory includes a spin-orbit coupling layer and a magnetoresistive tunnel junction located on the spin-orbit coupling layer. The magnetoresistive tunnel junction includes a first magnetic layer, a tunneling layer, and a second magnetic layer that are sequentially stacked from bottom to top, and each of the first magnetic layer and the second magnetic layer has perpendicular anisotropy. In a direction of a current in the spin-orbit coupling layer, defects are generated in a part of the magnetoresistive tunnel junction by an ion implantation process.

公开(公告)号：US09306003B2

公开(公告)日：2016-04-05

申请号：US14396709

申请日：2014-08-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jing Xu ,  Jiang Yan ,  Bangming Chen ,  Hongli Wang ,  Bo Tang ,  Zhaoyun Tang ,  Yefeng Xu ,  Chunlong Li ,  Mengmeng Yang

IPC: H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/0653 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78654 ,  H01L29/78687 ,  H01L29/78696

Abstract: A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.

Abstract translation: 一种半导体器件，包括：具有第一半导体材料的衬底; 在所述基板上的第二半导体层; 第二半导体层上的第三半导体层，并且是器件形成区域; 在第三半导体层的两侧和基板上的隔离结构; 以及在第三半导体层的源极和漏极区域之下以及隔离结构和第二半导体层的端部之间的绝缘层。