公开(公告)号：US20240071451A1

公开(公告)日：2024-02-29

申请号：US18261716

申请日：2021-01-21

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huai LIN ,  Guozhong XING ,  Zuheng WU ,  Long LIU ,  Di WANG ,  Cheng LU ,  Peiwen ZHANG ,  Changqing XIE ,  Ling LI ,  Ming LIU

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1655 ,  G11C11/1657

Abstract: The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.

公开(公告)号：US20230267990A1

公开(公告)日：2023-08-24

申请号：US18005101

申请日：2020-08-24

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qing LUO ,  Bing CHEN ,  Hangbing LV ,  Ming LIU ,  Cheng LU

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094 ,  H03K19/017

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4094 ,  H03K19/01742

Abstract: Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.