公开(公告)号：US20150332973A1

公开(公告)日：2015-11-19

申请号：US14652956

申请日：2013-07-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huicai ZHONG ,  Qingqing LIANG ,  Da YANG ,  Chao ZHAO

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088 ,  H01L21/265 ,  H01L29/423

CPC classification number: H01L21/823437 ,  H01L21/26533 ,  H01L21/28176 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/78

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) forming gate lines extending in a direction on a substrate; b) forming a photoresist layer that covers the semiconductor structure; patterning the photoresist layer to form openings across the gate lines; c) narrowing the openings by forming a self-assembly copolymer inside the openings; and d) cutting the gate lines via the openings to make the gate lines insulated at the openings. Through forming an additional layer on the inner wall of the openings of the photoresist layer, the method for manufacturing a semiconductor structure provided by the present invention manages to reduce the distance between the two opposite walls of the openings in the direction of gate width, namely, the method manages to reduce the distance between the ends of electrically isolated gates located on the same line where it is unnecessary to manufacture a cut mask whose lines are extremely fine. Working area is therefore saved, which accordingly improves integration level of semiconductor devices. In addition, the present invention further provides a semiconductor structure according to the method provided by the present invention.

Abstract translation: 本发明提供一种制造半导体结构的方法，其包括：a）形成沿衬底方向延伸的栅极线; b）形成覆盖半导体结构的光致抗蚀剂层; 图案化光致抗蚀剂层以在栅极线上形成开口; c）通过在开口内形成自组装共聚物来缩小开口; 以及d）经由所述开口切割所述栅极线以使所述栅极线在所述开口处绝缘。 通过在光致抗蚀剂层的开口的内壁上形成附加层，本发明提供的半导体结构的制造方法旨在减小开口方向的两个相对壁之间在栅极宽度方向上的距离，即 该方法旨在减少位于同一线路上的电隔离门的端部之间的距离，其中不需要制造线极细的切割掩模。 因此节省了工作区域，从而提高了半导体器件的集成度。 此外，本发明还提供根据本发明提供的方法的半导体结构。

公开(公告)号：US20190189523A1

公开(公告)日：2019-06-20

申请号：US16327973

申请日：2016-12-21

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU ,  Huicai ZHONG ,  Yanbo ZHANG

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66

Abstract: A semiconductor arrangement includes: a substrate; a plurality of fins formed on the substrate and extending in a first direction; a plurality of gate stacks formed on the substrate and extending in a second direction crossing the first direction and dummy gates composed of dielectric and extending in the second direction, wherein each of the gate stacks intersects at least one of the fins; and spacers formed on sidewalls of the gate stacks and sidewalls of the dummy gates, wherein spacers of at least a first one and a second one among the gate stacks and the dummy gates which are aligned in the second direction extend integrally, and at least some of the fins have ends abutting the dummy gates and substantially aligned with inner walls of corresponding ones of the spacers.

公开(公告)号：US20160163592A1

公开(公告)日：2016-06-09

申请号：US14943706

申请日：2015-11-17

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huicai ZHONG ,  Chao ZHAO ,  Huilong ZHU

IPC: H01L21/768

CPC classification number: H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49827

Abstract: In a method for manufacturing a semiconductor, a Through Silicon Via (TSV) template wafer and production wafers form a sandwich structure, in which the TSV template wafer has TSV structures uniformly distributed therein, for providing electrical connection between the production wafers to form 3D interconnection. The TSV template wafer is obtained by thinning a semiconductor wafer, which facilitates reducing the difficulty in etching and filling. Connection parts are provided on the TSV template wafer, for convenience of interconnection between the overlying and underlying production wafers, which facilitates reducing the difficulty in alignment and improving the convenience of design of electrical connection for 3D devices.

Abstract translation: 在制造半导体的方法中，透明硅（TSV）模板晶片和生产晶片形成夹层结构，其中TSV模板晶片具有均匀分布在其中的TSV结构，用于在生产晶片之间提供电连接以形成3D互连 。 通过减薄半导体晶片获得TSV模板晶片，这有助于降低蚀刻和填充的难度。 在TSV模板晶片上提供连接部件，以方便上层和下面的生产晶圆之间的互连，这有助于降低对准难度，并提高3D设备电气连接设计的便利性。

公开(公告)号：US20210020640A1

公开(公告)日：2021-01-21

申请号：US17039770

申请日：2020-09-30

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU ,  Yanbo ZHANG ,  Huicai ZHONG

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.

公开(公告)号：US20190304976A1

公开(公告)日：2019-10-03

申请号：US16461330

申请日：2016-12-21

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU ,  Yanbo ZHANG ,  Huicai ZHONG

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/033 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.