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    Method For Forming Gate-All-Around Nanowire Device
    1.
    发明申请
    Method For Forming Gate-All-Around Nanowire Device 审中-公开

    公开(公告)号：US20200335596A1

    公开(公告)日：2020-10-22

    申请号：US16561192

    申请日：2019-09-05

    Applicant: Institute of Microelectronics, Chinese Academy of Sciences

    Inventor： Huaxiang YIN ,  Jiaxin YAO ,  Qingzhu ZHANG ,  Zhaohao ZHANG ,  Tianchun YE

    IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L21/225

    Abstract: A gate-all-around nanowire device and a method for forming the gate-all-around nanowire device. A first fin and a dielectric layer on the first fin are formed on a substrate. The first fin includes the at least one first epitaxial layer and the at least one second epitaxial layer that are alternately stacked. The dielectric layer exposes a channel region of the first fin. A doping concentration at a lateral surface of the channel region and a doping concentration at a central region of the channel region are different from each other in the at least one second epitaxial layer. After the at least one first epitaxial layer is removed from the channel region, the at least one second epitaxial layer in the channel region serves as at least one nanowire. A gate surrounding the at least one nanowire is formed.

    3DS FET AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    3DS FET AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20240379794A1

    公开(公告)日：2024-11-14

    申请号：US18462613

    申请日：2023-09-07

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Huaxiang YIN ,  Peng ZHAO ,  Zhenhua WU ,  Jiaxin YAO

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

    Abstract: Provided are a three-dimensional stack field-effect transistor (3DS FET) and a method of manufacturing the same. According to embodiments, the 3DS FET includes: a lower active region arranged on a substrate, an upper active region above the lower active region and a gate stack. The lower active region includes: a fin extending in a first direction on the substrate, and lower source/drain portions at two opposite ends of the fin in the first direction, respectively. The upper active region includes: one or more nanosheets, a lowest nanosheet is spaced apart from the fin in a vertical direction relative to the substrate, and upper source/drain portions at two opposite ends of the one or more nanosheets in the first direction, respectively. The gate stack extends in a second direction intersecting with the first direction so as to intersect with the fin and the one or more nanosheets.

    COMPUTING-IN-MEMORY CIRCUIT AND SRAM MEMORY DEVICE
    5.
    发明申请
    COMPUTING-IN-MEMORY CIRCUIT AND SRAM MEMORY DEVICE 有权

    公开(公告)号：US20250069653A1

    公开(公告)日：2025-02-27

    申请号：US18947250

    申请日：2024-11-14

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Huaxiang YIN ,  Xuexiang ZHANG ,  Jiaxin YAO

    IPC: G11C11/419 ,  G11C11/418 ,  H03K19/20

    Abstract: The computing-in-memory circuit includes: an SRAM memory cell array including at least one memory cell connected between a first bit line and a second bit line, the memory cell includes a first inverter and a second inverter cross-coupled with each other, and the first inverter and the second inverter have an asymmetric configuration with respect to each other; a control circuit configured to: receive a first input signal, a second input signal and an operation mode control signal, process the first input signal and the second input signal according to operation mode control signal, so as to obtain a processed first input signal and a processed second input signal, and apply the processed first input signal and the processed second input signal to the first bit line and the second bit line, respectively; and a readout circuit configured to read out data stored in memory cell from the memory cell.

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