公开(公告)号：US20200335596A1

公开(公告)日：2020-10-22

申请号：US16561192

申请日：2019-09-05

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang YIN ,  Jiaxin YAO ,  Qingzhu ZHANG ,  Zhaohao ZHANG ,  Tianchun YE

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L21/225

Abstract: A gate-all-around nanowire device and a method for forming the gate-all-around nanowire device. A first fin and a dielectric layer on the first fin are formed on a substrate. The first fin includes the at least one first epitaxial layer and the at least one second epitaxial layer that are alternately stacked. The dielectric layer exposes a channel region of the first fin. A doping concentration at a lateral surface of the channel region and a doping concentration at a central region of the channel region are different from each other in the at least one second epitaxial layer. After the at least one first epitaxial layer is removed from the channel region, the at least one second epitaxial layer in the channel region serves as at least one nanowire. A gate surrounding the at least one nanowire is formed.

公开(公告)号：US20200211910A1

公开(公告)日：2020-07-02

申请号：US16722406

申请日：2019-12-20

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang YIN ,  Qingzhu ZHANG ,  Xiang LIN

IPC: H01L21/84 ,  H01L27/12 ,  H01L23/522

Abstract: A multilayer MOS device and a method for manufacturing the same. The manufacturing method includes: providing a MOS device including n layers, where n is a natural number greater than zero; forming a semiconductor layer on the MOS device including n layers; forming a gate oxide layer and a dummy gate on the semiconductor layer sequentially, where at least a part of the gate oxide layer is located between the dummy gate and the semiconductor layer; forming a metal silicide layer in the semiconductor layer at two sides of the dummy gate, to obtain a MOS device of an (n+1)-th layer, where the metal silicide layer serves as a metallized source-drain region or the metal silicide layer is doped to form a metalized source-drain region; and connecting a MOS device of an n-th layer of the n layers with the MOS device of the (n+1)-th layer via metallic interconnection.

公开(公告)号：US20160086946A1

公开(公告)日：2016-03-24

申请号：US14721386

申请日：2015-05-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang YIN ,  Hong YANG ,  Qingzhu ZHANG ,  Qiuxia XU

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/0924

Abstract: An CMOS device comprises a plurality of NMOS transistors and a plurality of PMOS transistors, each of which comprises a gate stack constituted of a gate insulating layer and a gate metal layer on a substrate, a source/drain region in the substrate on both sides of the gate stack and a channel region below the gate stack, wherein the gate metal layer of each NMOS transistor comprising a first barrier layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the gate metal layer of each PMOS transistor comprising a first barrier layer, a PMOS work function adjusting layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the first barrier layer in the gate metal layer of the NMOS transistor and the first barrier layer in the gate metal layer of the PMOS transistor contain a doping ion to finely adjust the work function. The semiconductor device and the method for manufacturing the same according to the present disclosure utilize the sacrificial layer to diffuse impurity to the barrier layer so that the adjusting accuracy of the threshold voltage may be effectively improved, thereby facilitating in improving the whole performance of the device.

Abstract translation: CMOS器件包括多个NMOS晶体管和多个PMOS晶体管，每个PMOS晶体管包括由衬底上的栅极绝缘层和栅极金属层构成的栅极堆叠，在衬底的两侧的衬底中的源极/漏极区域 栅极堆叠和栅极堆叠下方的沟道区，其中每个NMOS晶体管的栅极金属层包括第一势垒层，NMOS功函数调节层，第二势垒层和填充层，并且其中栅极金属层 每个PMOS晶体管包括第一阻挡层，PMOS功函数调整层，NMOS功函数调整层，第二势垒层和填充层，并且其中NMOS晶体管的栅极金属层中的第一势垒层和 PMOS晶体管的栅极金属层中的第一势垒层含有掺杂离子以微调功函数。 根据本公开的半导体器件及其制造方法利用牺牲层将杂质扩散到阻挡层，从而可以有效地提高阈值电压的调整精度，从而有助于提高器件的整体性能 。

公开(公告)号：US20250133773A1

公开(公告)日：2025-04-24

申请号：US18915723

申请日：2024-10-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qingzhu ZHANG ,  Lianlian LI ,  Anyan DU ,  Huaxiang YIN ,  Lei CAO ,  Jiaxin YAO ,  Zhaohao ZHANG ,  Qingkun LI ,  Guanqiao SANG

IPC: H01L29/423 ,  H01L21/822 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: The present disclosure relates to a stacked nanosheet gate-all-around device with an air spacer and a method of manufacturing a stacked nanosheet gate-all-around device with an air spacer. The stacked nanosheet gate-all-around device with the air spacer includes: a substrate with a shallow trench isolation structure on a surface of the substrate; a nanosheet stacking portion provided above the substrate, where the nanosheet stacking portion includes a stack formed by a plurality of nanosheets, and the stack formed by the nanosheets constitutes a plurality of conductive channels; a gate-all-around surrounding the nanosheet stacking portion; and a source/drain region located on two opposite sides of the nanosheet stacking portion, where an empty spacer is provided between the source/drain region and the gate-all-around, where an interior of the empty spacer is filled with at least one of air, a reducing gas, or an inert gas.

公开(公告)号：US20250069653A1

公开(公告)日：2025-02-27

申请号：US18947250

申请日：2024-11-14

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang YIN ,  Xuexiang ZHANG ,  Jiaxin YAO

IPC: G11C11/419 ,  G11C11/418 ,  H03K19/20

Abstract: The computing-in-memory circuit includes: an SRAM memory cell array including at least one memory cell connected between a first bit line and a second bit line, the memory cell includes a first inverter and a second inverter cross-coupled with each other, and the first inverter and the second inverter have an asymmetric configuration with respect to each other; a control circuit configured to: receive a first input signal, a second input signal and an operation mode control signal, process the first input signal and the second input signal according to operation mode control signal, so as to obtain a processed first input signal and a processed second input signal, and apply the processed first input signal and the processed second input signal to the first bit line and the second bit line, respectively; and a readout circuit configured to read out data stored in memory cell from the memory cell.

公开(公告)号：US20250031417A1

公开(公告)日：2025-01-23

申请号：US18543652

申请日：2023-12-18

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang YIN ,  Qingzhu ZHANG ,  Yadong ZHANG ,  Jiaxin YAO

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device and a method for manufacturing the same. The method comprise: forming a first field-effect transistor (FET) disposed on a substrate and a first isolation layer disposed on the first FET; forming a first through hole in the first isolation layer, where a metal layer is deposited in the first through hole and is electrically connected to the first FET; forming a second isolation layer, which is disposed on the first isolation layer and the metal layer; and forming a second FET which is disposed on the second isolation layer, where a second through hole is disposed in the second FET and the second isolation layer, a metal material filled in the second through hole serves as a first contact plug, and the first contact plug is electrically connected to the metal layer. The metal layer serves as a power distribution network for both FETs.

公开(公告)号：US20210151561A1

公开(公告)日：2021-05-20

申请号：US16824810

申请日：2020-03-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang LI ,  Xiaohong CHENG ,  Qingzhu ZHANG ,  Huaxiang YIN ,  Wenwu WANG

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84

Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.

公开(公告)号：US20210193822A1

公开(公告)日：2021-06-24

申请号：US17029495

申请日：2020-09-23

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang YIN ,  Qingzhu ZHANG ,  Renren XU

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8238

Abstract: A method for manufacturing a semiconductor device is provided. A first substrate and at least one second substrate are provided. A single crystal lamination structure is fonned on the first substrate. The single crystal lamination structure includes at least one hetero-material layer and at least one channel material layer that are alternately laminated, each of the at least one hetero-material layer is bonded to an adjacent one of the at least one channel material layer at a side away from the first substrate, and each of the at least one channel material layer is formed from one of the at least one second substrate. At least one layer of nanowire or nanosheet is formed from the single crystal lamination structure. A gate dielectric layer and a gate which surround each of the at least one layer of nanowire or nanosheet is formed. A semiconductor device is also provided.

公开(公告)号：US20160211351A1

公开(公告)日：2016-07-21

申请号：US15001087

申请日：2016-01-19

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Guilei WANG ,  Hushan CUI ,  Huaxiang YIN ,  Junfeng LI ,  Chao ZHAO

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/67 ,  C30B25/16 ,  C30B25/08 ,  C30B25/12 ,  C30B25/14 ,  H01L21/306 ,  C23C16/02

CPC classification number: H01L29/66795 ,  C30B25/08 ,  C30B25/12 ,  C30B25/14 ,  C30B25/16 ,  C30B35/00 ,  H01L21/67167

Abstract: An apparatus and a method for epitaxially growing sources and drains of a FinFET device. The apparatus comprises: a primary chamber; a wafer-loading chamber; a transfer chamber provided with a mechanical manipulator for transferring the wafer; an etching chamber for removing a natural oxide layer on the surface of the wafer and provided with a graphite base for positioning the wafer; at least one epitaxial reaction chamber; a gas distribution device for supplying respective gases to the primary chamber, the wafer loading chamber, the transfer chamber, the etching chamber and the epitaxial reaction chamber; and a vacuum device. The wafer loading, transfer, etching, and epitaxial reaction chambers are all positioned within the primary chamber. The apparatus integrates the etching chamber and epitaxial reaction chamber to remove the natural oxide layer on the surface of the wafer in a condition of isolating water and oxygen before the epitaxial reaction has occurred.

Abstract translation: 一种用于外延生长FinFET器件的源极和漏极的装置和方法。 该装置包括：主室; 晶片加载室; 传送室，设置有用于传送晶片的机械操纵器; 用于去除晶片表面上的自然氧化物层并设置有用于定位晶片的石墨基底的蚀刻室; 至少一个外延反应室; 用于向主室，晶片装载室，传送室，蚀刻室和外延反应室供应各种气体的气体分配装置; 和真空装置。 晶片装载，转移，蚀刻和外延反应室都位于主室内。 在外延反应发生之前，在分离水和氧的条件下，将蚀刻室和外延反应室集成在晶片表面上去除天然氧化物层。

公开(公告)号：US20210384080A1

公开(公告)日：2021-12-09

申请号：US17004173

申请日：2020-08-27

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Guilei WANG ,  Henry H. RADAMSON ,  Zhenzhen KONG ,  Junjie LI ,  Jinbiao LIU ,  Junfeng LI ,  Huaxiang YIN

IPC: H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device and a method for manufacturing the semiconductor device. Multiple stacks and an isolation structure among the multiple stacks are formed on a substrate. Each stack includes a first doping layer, a channel layer and a second doping layer. For each stack, the channel layer is laterally etched from at least one sidewall of said stack to form a cavity located between the first doping layer and the second doping layer, and a gate dielectric layer and a gate layer are formed in the cavity. A first sidewall of each stack is contact with the isolation structure, and the at least one sidewall does not include the first side wall. Costly high-precision etching is not necessary, and therefore a device with a small size and a high performance can be achieved with a simple process and a low cost. Diversified device structures can be provided on requirement.