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公开(公告)号:US11411091B2
公开(公告)日:2022-08-09
申请号:US16954776
申请日:2019-10-30
Inventor: Huaxiang Yin , Tianchun Ye , Qingzhu Zhang , Jiaxin Yao
IPC: H01L29/423 , H01L29/06 , H01L21/8238 , H01L29/66 , H01L29/786 , H01L27/092
Abstract: A method for manufacturing a stacked gate-all-around nano-sheet CMOS device, including: providing a substrate with a fin structure, where a channel layer for an NMOS is a sacrificial layer for a PMOS, a channel layer for the PMOS is a sacrificial layer for the NMOS; and mobility of holes in the second material is greater than mobility of holes in the first material; forming a dummy gate stack extending across the fin structure; forming source-or-drain regions in the fin structure at two sides of the dummy gate stack; removing the dummy gate stack and the sacrificial layers covered by the dummy gate stack, to expose a surface of a part of the channel layer that is located between the source-or-drain regions, where a nano-sheet array is formed by the channel layer with the exposed surface; and forming a gate stack structure surrounding each nano sheet in the nano-sheet array.
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公开(公告)号:US11594608B2
公开(公告)日:2023-02-28
申请号:US16561192
申请日:2019-09-05
Inventor: Huaxiang Yin , Jiaxin Yao , Qingzhu Zhang , Zhaohao Zhang , Tianchun Ye
IPC: H01L29/423 , H01L21/225 , H01L29/40 , H01L29/66 , H01L29/78
Abstract: A gate-all-around nanowire device and a method for forming the gate-all-around nanowire device. A first fin and a dielectric layer on the first fin are formed on a substrate. The first fin includes the at least one first epitaxial layer and the at least one second epitaxial layer that are alternately stacked. The dielectric layer exposes a channel region of the first fin. A doping concentration at a lateral surface of the channel region and a doping concentration at a central region of the channel region are different from each other in the at least one second epitaxial layer. After the at least one first epitaxial layer is removed from the channel region, the at least one second epitaxial layer in the channel region serves as at least one nanowire. A gate surrounding the at least one nanowire is formed.
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