公开(公告)号：US20150255609A1

公开(公告)日：2015-09-10

申请号：US14434437

申请日：2012-12-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Miao Xu ,  Qingqing Liang ,  Haizhou Yin

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/10 ,  H01L21/306 ,  H01L21/308 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/161 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L29/7851 ,  H01L21/02274 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6681 ,  H01L29/7848

Abstract: Provided are semiconductor devices and methods for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; implanting ions into a portion of the substrate beneath the fin, to form a punch-through stopper; forming a gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; and forming a third semiconductor layer on the substrate, to form source/drain regions.

Abstract translation: 提供半导体器件及其制造方法。 示例性方法可以包括：在衬底上顺序地形成第一半导体层和第二半导体层; 图案化第二半导体层和第一半导体层以形成翅片; 在所述衬底上形成隔离层，其中所述隔离层暴露所述第一半导体层的一部分; 将离子注入翅片下面的基底的一部分，以形成穿通塞子; 形成跨越隔离层上的翅片的栅极堆叠; 以所述栅极叠层为掩模选择性蚀刻所述第二半导体层，以露出所述第一半导体层; 选择性地蚀刻第一半导体层，以在第二半导体层下面形成空隙; 以及在所述衬底上形成第三半导体层以形成源/漏区。

公开(公告)号：US10263111B2

公开(公告)日：2019-04-16

申请号：US14647736

申请日：2012-12-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Miao Xu

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/308 ,  H01L29/08 ,  H01L21/265 ,  H01L29/165

Abstract: A FinFET and a method for manufacturing the same are provided. The method includes: patterning a semiconductor substrate to form a ridge; performing ion implantation such that a doped punch-through-stopper layer is formed in the ridge and a semiconductor fin is formed by a portion of the semiconductor substrate disposed above the doped punch-through-stopper layer; forming a gate stack intersecting the semiconductor fin, the gate stack comprising a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor fin; forming a gate spacer surrounding the gate conductor; and forming source and drain regions in portions of the semiconductor fin at opposite sides of the gate stack.

公开(公告)号：US20150200275A1

公开(公告)日：2015-07-16

申请号：US14585053

申请日：2014-12-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Miao Xu ,  Qingqing Liang ,  Haizhou Yin

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/4925 ,  H01L29/785

Abstract: A FinFET with reduced leakage between source and drain regions, and a method for manufacturing the FinFET are disclosed. In one aspect, the method includes forming, on a semiconductor substrate, at least two openings to define a semiconductor fin. The method also includes forming a gate dielectric layer that conformally covers the fin and the openings. The method also includes forming, within the openings, a first gate conductor adjacent to the bottom of the fin. The method also includes forming, within the openings, an insulating isolation layer on the first gate conductor. The method also includes forming a second gate conductor on the fin and on the insulating isolation layer adjacent to the top of the fin. The method also includes forming spacers on sidewalls of the second gate conductor. The method also includes forming a source region and a drain region in the fin.

Abstract translation: 公开了一种在源极和漏极区域之间具有减小的漏电流的FinFET以及制造FinFET的方法。 一方面，该方法包括在半导体衬底上形成至少两个开口以限定半导体鳍片。 该方法还包括形成保形地覆盖翅片和开口的栅极电介质层。 该方法还包括在开口内形成与鳍片的底部相邻的第一栅极导体。 该方法还包括在开口内形成第一栅极导体上的绝缘隔离层。 该方法还包括在翅片上形成第二栅极导体，并且在与鳍片的顶部相邻的绝缘隔离层上形成第二栅极导体。 该方法还包括在第二栅极导体的侧壁上形成间隔物。 该方法还包括在散热片中形成源极区域和漏极区域。

公开(公告)号：US20150325699A1

公开(公告)日：2015-11-12

申请号：US14647736

申请日：2012-12-07

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Miao Xu

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/308 ,  H01L21/265 ,  H01L21/311 ,  H01L21/02 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02274 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/31111 ,  H01L29/0843 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7842 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A FinFET and a method for manufacturing the same are provided. The method includes: patterning a semiconductor substrate to form a ridge; performing ion implantation such that a doped punch-through-stopper layer is formed in the ridge and a semiconductor fin is formed by a portion of the semiconductor substrate disposed above the doped punch-through-stopper layer; forming a gate stack intersecting the semiconductor fin, the gate stack comprising a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor fin; forming a gate spacer surrounding the gate conductor; and forming source and drain regions in portions of the semiconductor fin at opposite sides of the gate stack.

Abstract translation: 提供FinFET及其制造方法。 该方法包括：图案化半导体衬底以形成脊; 进行离子注入，使得在所述脊中形成掺杂的穿通阻挡层，并且通过设置在所述掺杂穿通阻挡层上方的所述半导体衬底的一部分形成半导体鳍; 形成与所述半导体鳍片相交的栅极堆叠，所述栅极堆叠包括栅极导体和将所述栅极导体与所述半导体鳍片隔离的栅极介质; 形成围绕所述栅极导体的栅极间隔; 以及在栅叠层的相对侧的半导体鳍片的部分中形成源区和漏区。

公开(公告)号：US09691624B2

公开(公告)日：2017-06-27

申请号：US14442890

申请日：2012-12-14

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Miao Xu ,  Jun Luo ,  Chunlong Li ,  Guilei Wang

IPC: H01L21/336 ,  H01L21/84 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L21/30625 ,  H01L21/31053 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795

Abstract: Provided is a method for manufacturing a fin structure. The method may include forming an initial fin on a substrate, forming a dielectric layer on the substrate to cover the initial fin, planarizing the dielectric layer by sputtering, and further etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion serves as a fin.

公开(公告)号：US09349867B2

公开(公告)日：2016-05-24

申请号：US14434437

申请日：2012-12-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Miao Xu ,  Qingqing Liang ,  Haizhou Yin

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L21/02274 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6681 ,  H01L29/7848

Abstract: Provided are semiconductor devices and methods for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; implanting ions into a portion of the substrate beneath the fin, to form a punch-through stopper; forming a gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; and forming a third semiconductor layer on the substrate, to form source/drain regions.

Abstract translation: 提供半导体器件及其制造方法。 示例性方法可以包括：在衬底上顺序地形成第一半导体层和第二半导体层; 图案化第二半导体层和第一半导体层以形成翅片; 在所述衬底上形成隔离层，其中所述隔离层暴露所述第一半导体层的一部分; 将离子注入翅片下面的基底的一部分，以形成穿通塞子; 形成跨越隔离层上的翅片的栅极堆叠; 以所述栅极叠层为掩模选择性蚀刻所述第二半导体层，以露出所述第一半导体层; 选择性地蚀刻第一半导体层，以在第二半导体层下面形成空隙; 以及在所述衬底上形成第三半导体层以形成源/漏区。

公开(公告)号：US20150294879A1

公开(公告)日：2015-10-15

申请号：US14442890

申请日：2012-12-14

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Miao Xu ,  Jun Luo ,  Chunlong Li ,  Guilei Wang

IPC: H01L21/306 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L21/30625 ,  H01L21/31053 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795

Abstract: Provided is a method for manufacturing a fin structure. The method may include forming an initial fin on a substrate, forming a dielectric layer on the substrate to cover the initial fin, planarizing the dielectric layer by sputtering, and further etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion serves as a fin.

Abstract translation: 提供一种翅片结构的制造方法。 该方法可以包括在衬底上形成初始翅片，在衬底上形成电介质层以覆盖初始翅片，通过溅射对电介质层进行平面化，并进一步蚀刻介电层以暴露初始鳍片的一部分，其中 露出部分作为翅片。

公开(公告)号：US10008602B2

公开(公告)日：2018-06-26

申请号：US14436366

申请日：2012-11-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Miao Xu ,  Haizhou Yin ,  Qingqing Liang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L21/02 ,  H01L21/265 ,  H01L21/308 ,  H01L21/311 ,  H01L29/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/311 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7848

Abstract: A semiconductor device and a method of manufacturing the same are provided, wherein an example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; forming a sacrificial gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the sacrificial gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; filling the void with a dielectric material; forming a third semiconductor layer on the substrate, to form source/drain regions; and forming a gate stack to replace the sacrificial gate stack.

公开(公告)号：US09679962B2

公开(公告)日：2017-06-13

申请号：US14814022

申请日：2015-07-30

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Miao Xu ,  Huilong Zhu ,  Lichuan Zhao

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/82 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/0638 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545

Abstract: There is provided a method of manufacturing a Fin Field Effect Transistor (FinFET). The method may include: forming a fin on a semiconductor substrate; forming a dummy device including a dummy gate on the fin; forming an interlayer dielectric layer to cover regions except for the dummy gate; removing the dummy gate to form an opening; implanting ions to form a Punch-Through-Stop Layer (PTSL) in a portion of the fin directly under the opening, while forming reflection doped layers in portions of the fin on inner sides of source/drain regions; and forming a replacement gate in the opening.

公开(公告)号：US20150287828A1

公开(公告)日：2015-10-08

申请号：US14436366

申请日：2012-11-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Miao Xu ,  Haizhou Yin ,  Qingqing Liang

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L29/161 ,  H01L21/308

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/311 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7848

Abstract: A semiconductor device and a method of manufacturing the same are provided, wherein an example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; forming a sacrificial gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the sacrificial gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; filling the void with a dielectric material; forming a third semiconductor layer on the substrate, to form source/drain regions; and forming a gate stack to replace the sacrificial gate stack.

Abstract translation: 提供一种半导体器件及其制造方法，其中示例性方法可以包括：在衬底上依次形成第一半导体层和第二半导体层; 图案化第二半导体层和第一半导体层以形成翅片; 在所述衬底上形成隔离层，其中所述隔离层暴露所述第一半导体层的一部分; 形成跨过隔离层上的翅片的牺牲栅极堆叠; 用所述牺牲栅极堆叠作为掩模选择性地蚀刻所述第二半导体层，以暴露所述第一半导体层; 选择性地蚀刻第一半导体层，以在第二半导体层下方形成空隙; 用介电材料填充空隙; 在所述衬底上形成第三半导体层，以形成源极/漏极区域; 以及形成栅极堆叠以替代牺牲栅极堆叠。