公开(公告)号：US20240120382A1

公开(公告)日：2024-04-11

申请号：US18262193

申请日：2021-11-26

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY ,  INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Qi Wang

IPC: H01L29/08 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H10B12/00

CPC classification number: H01L29/0847 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78642 ,  H01L29/78696 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: A storage device includes a substrate, a storage unit array, and word lines extending in the first direction. The storage unit array includes storage units arranged along a first direction and a second direction. Each storage unit includes: an active region extending in a third direction and including a vertical stack of first source/drain, channel and second source/drain layers, and a gate stack between the first and second source/drain layers in a vertical direction and sandwiching the channel layer from at least two opposite sides. First source/drain layers of each column are continuous to form a bit line extending in the second direction in a zigzag shape. Each word line extends in the first direction to intersect the active regions of a respective row, and is electrically connected to the gate stack of each storage unit on two opposite sides of the channel layer.

公开(公告)号：US20240233810A9

公开(公告)日：2024-07-11

申请号：US18548035

申请日：2021-11-26

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY ,  INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qi Wang ,  Huilong Zhu

IPC: G11C11/408 ,  G11C11/4097

CPC classification number: G11C11/4085 ,  G11C11/4097

Abstract: A storage device is provided, including: a substrate; word lines extending in a first direction; bit lines extending in a second direction perpendicular to the first direction; and a storage unit including a plurality of storage units, each of which is electrically connected to a word line and a bit line. Each storage unit includes: an active region extending in a third direction inclined with the first direction; a vertical stack of a first source/drain layer, a channel layer and a second source/drain layer; and gate stacks between the first source/drain layer and the second source/drain layer, and on opposite sides of the channel layer in a fourth direction orthogonal to the third direction, to sandwich the channel layer. The word line corresponding to each storage unit extends across the storage unit in the first direction to be electrically connected to the gate stacks on opposite sides.

公开(公告)号：US20240135986A1

公开(公告)日：2024-04-25

申请号：US18548035

申请日：2021-11-26

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY ,  INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qi Wang ,  Huilong Zhu

IPC: G11C11/408 ,  G11C11/4097

CPC classification number: G11C11/4085 ,  G11C11/4097

Abstract: A storage device is provided, including: a substrate; word lines extending in a first direction; bit lines extending in a second direction perpendicular to the first direction; and a storage unit including a plurality of storage units, each of which is electrically connected to a word line and a bit line. Each storage unit includes: an active region extending in a third direction inclined with the first direction; a vertical stack of a first source/drain layer, a channel layer and a second source/drain layer; and gate stacks between the first source/drain layer and the second source/drain layer, and on opposite sides of the channel layer in a fourth direction orthogonal to the third direction, to sandwich the channel layer. The word line corresponding to each storage unit extends across the storage unit in the first direction to be electrically connected to the gate stacks on opposite sides.

公开(公告)号：US20230120804A1

公开(公告)日：2023-04-20

申请号：US17907048

申请日：2020-03-23

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Qi Wang ,  Yiyang Jiang ,  Qianhui Li ,  Zongliang Huo

IPC: H03M13/11 ,  H03M13/15 ,  H03M13/39

Abstract: The method includes: reading a memory cell having a encoded information bit, so as to obtain an LLR value of a current memory cell with reference to a pre-established LLR table according to a storage time, a threshold voltage partition and a comprehensive distribution corresponding to the current memory cell during reading; and performing a soft decoding operation on a codeword in the memory cell having the encoded information bit according to the read LLR value of the current memory cell, wherein the comprehensive distribution of the current memory cell is determined according to an influence of a memory cell adjacent to the current memory cell on a distribution of the current memory cell; an input of the pre-established LLR table comprises a storage time, a threshold voltage partition and a comprehensive distribution, and an output of the pre-established LLR table comprises an LLR value.

公开(公告)号：US12197282B2

公开(公告)日：2025-01-14

申请号：US18553929

申请日：2021-04-08

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qianhui Li ,  Qi Wang ,  Liu Yang ,  Yiyang Jiang ,  Xiaolei Yu ,  Jing He ,  Zongliang Huo ,  Tianchun Ye

IPC: G06F11/10 ,  G06F11/14

Abstract: A data recovery method for a flash memory includes: reading data from the flash memory by using preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step size according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, and repeating the operation of calculating a check node error rate corresponding to the data to operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, until the check node error rate is minimum; and selecting a read voltage corresponding to the minimum check node error rate to read data from the flash memory, so as to perform data recovery.

公开(公告)号：US12088323B2

公开(公告)日：2024-09-10

申请号：US18254377

申请日：2020-11-25

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qi Wang ,  Yiyang Jiang ,  Qianhui Li ,  Zongliang Huo ,  Tianchun Ye

IPC: H03M13/39 ,  G11C29/12 ,  G11C29/42 ,  G11C29/46

CPC classification number: H03M13/3905 ,  G11C29/1201 ,  G11C29/42 ,  G11C29/46

Abstract: A read-write method includes: sequentially writing, in a first direction, a code word obtained by information-bit encoding into a target memory cell in each layer of memory cell array in the three-dimensional memory; randomly reading the target memory cell in each layer of memory cell array, or sequentially reading the target memory cell in each layer of memory cell array in a second direction; and determining an LLR value of a current target memory cell according to a storage time corresponding to the current target memory cell when reading, a threshold voltage partition corresponding to the current target memory cell when reading, a comprehensive distribution state corresponding to the current target memory cell when reading, and a pre-established LLR table, so as to perform a soft decoding operation on the code word in the current target memory cell based on the LLR value of the current target memory cell.

公开(公告)号：US12068757B2

公开(公告)日：2024-08-20

申请号：US17907048

申请日：2020-03-23

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Qi Wang ,  Yiyang Jiang ,  Qianhui Li ,  Zongliang Huo

IPC: H03M13/11 ,  H03M13/15 ,  H03M13/39 ,  G06F11/00 ,  G11C29/52 ,  H03M13/25 ,  H03M13/29 ,  H03M13/37 ,  H03M13/45

CPC classification number: H03M13/1111 ,  H03M13/154 ,  H03M13/3927 ,  G06F11/00 ,  G11C29/52 ,  H03M13/1108 ,  H03M13/255 ,  H03M13/2948 ,  H03M13/3746 ,  H03M13/45

Abstract: The method includes: reading a memory cell having a encoded information bit, so as to obtain an LLR value of a current memory cell with reference to a pre-established LLR table according to a storage time, a threshold voltage partition and a comprehensive distribution corresponding to the current memory cell during reading; and performing a soft decoding operation on a codeword in the memory cell having the encoded information bit according to the read LLR value of the current memory cell, wherein the comprehensive distribution of the current memory cell is determined according to an influence of a memory cell adjacent to the current memory cell on a distribution of the current memory cell; an input of the pre-established LLR table comprises a storage time, a threshold voltage partition and a comprehensive distribution, and an output of the pre-established LLR table comprises an LLR value.

公开(公告)号：US20240038318A1

公开(公告)日：2024-02-01

申请号：US18254377

申请日：2020-11-25

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qi Wang ,  Yiyang Jiang ,  Qianhui Li ,  Zongliang Huo ,  Tianchun Ye

IPC: G11C29/42 ,  G11C29/46 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/46 ,  G11C29/1201

Abstract: A read-write method includes: sequentially writing, in a first direction, a code word obtained by information-bit encoding into a target memory cell in each layer of memory cell array in the three-dimensional memory; randomly reading the target memory cell in each layer of memory cell array, or sequentially reading the target memory cell in each layer of memory cell array in a second direction; and determining an LLR value of a current target memory cell according to a storage time corresponding to the current target memory cell when reading, a threshold voltage partition corresponding to the current target memory cell when reading, a comprehensive distribution state corresponding to the current target memory cell when reading, and a pre-established LLR table, so as to perform a soft decoding operation on the code word in the current target memory cell based on the LLR value of the current target memory cell.