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公开(公告)号：US20170162398A1
公开(公告)日：2017-06-08
申请号：US15060406
申请日：2016-03-03
Inventor： Xinyu LIU , Sen HUANG , Xinhua WANG , Ke WEI
IPC: H01L21/306 , H01L29/417 , H01L29/06 , H01L21/308 , H01L29/423
CPC classification number: H01L21/30621 , H01L21/3081 , H01L29/0649 , H01L29/2003 , H01L29/417 , H01L29/41766 , H01L29/4236 , H01L29/66462 , H01L29/7786
Abstract: A low-damage etching method for a III-Nitride structure is disclosed. The method comprises: forming an etching mask on the III-Nitride structure, which is formed on a substrate; and etching the III-Nitride with the etching mask, wherein a temperature of the substrate changes dynamically or is kept at a constant temperature point between 200° C. and 700° C. during the etching.
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2.发明申请公开(公告)号：US20190362966A1
公开(公告)日：2019-11-28
申请号：US16234303
申请日：2018-12-27
Inventor： Xinyu LIU , Yidan TANG , Shengkai WANG , Yun BAI , Chengyue YANG
IPC: H01L21/02
Abstract: A method of manufacturing a grooved-gate MOSFET device based on a two-step microwave plasma oxidation, including: etching a grooved gate, and oxidizing silicon carbide on a surface of the grooved gate to silicon dioxide by microwave plasma to form a grooved-gate oxide layer, the step of forming the grooved-gate oxide layer including: placing a silicon carbide substrate subjected to the grooved gate etching in a microwave plasma generating device; introducing a first oxygen-containing gas, heating generated oxygen plasma to a first temperature at a first heating rate, and performing low-temperature plasma oxidation at the first temperature and a first pressure; heating the oxygen plasma to a second temperature at a second heating rate, introducing a second oxygen-containing gas, and performing high-temperature plasma oxidation at the second temperature and a second pressure until a predetermined thickness of silicon dioxide is formed; stopping introduction of the oxygen-containing gas, and completing the reaction.
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3.发明公开公开(公告)号：US20240355921A1
公开(公告)日：2024-10-24
申请号：US18238947
申请日：2023-08-28
Inventor： Sen HUANG , Qimeng JIANG , Xinyue DAI , Xinhua WANG , Xinyu LIU
IPC: H01L29/778 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/66
CPC classification number: H01L29/7789 , H01L29/08 , H01L29/41725 , H01L29/4236 , H01L29/66462 , H01L29/7783
Abstract: The folded channel gallium nitride based field-effect transistor includes: a base layer; a multi-heterojunction layer, including a channel layer and a barrier layer alternatingly stacked from bottom to top on a gallium nitride semi-insulating layer; a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove; a current collapse suppression structure formed on the multi-heterojunction layer on another side of the channel region; a source electrode and a drain electrode that are respectively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer; a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; and a connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer.
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4.发明申请公开(公告)号：US20210043761A1
公开(公告)日：2021-02-11
申请号：US16868708
申请日：2020-05-07
Inventor： Sen HUANG , Xinhua WANG , Ke WEI , Xinyu LIU , Wen SHI
IPC: H01L29/778 , H01L29/20 , H01L29/66 , G01N27/414
Abstract: A detector based on a gallium nitride-based enhancement-mode device and a manufacturing method thereof. The detector is a gas or solution detector. When the detector is used in electrolyte solution detection, electrolyte solution is located in the gate opening region and directly contacts the thin barrier layer to form a contact interface. The electrolyte solution affects interface charges at the contact interface, leading to a change in a concentration of the two-dimensional electron gas, and further a change in a current between the source and the drain. When the detector is used in a hydrogen-containing gas detection, the H concentration of the hydrogen-containing gas affects interface charges at the contact interface between the gate and the thin barrier layer, leading to a change in a concentration of the two-dimensional electron gas, and further a change in the current between the source and the drain.
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Patent Agency Ranking
公开(公告)号：US20200152451A1
公开(公告)日：2020-05-14
申请号：US16287902
申请日：2019-02-27
Inventor： Xinyu LIU , Shengkai WANG , Yun BAI , Yidan TANG , Zhonglin HAN , Xiaoli TIAN , Hong CHEN , Chengyue YANG
Abstract: A method for oxidizing a silicon carbide based on microwave plasma at an AC voltage, including: step one, providing a silicon carbide substrate, and placing the silicon carbide substrate in a microwave plasma generating device; step two, introducing oxygen-containing gas to generate oxygen plasma at an AC voltage; step three, controlling movements of oxygen ions and electrons in the oxygen plasma by the AC voltage to generate an oxide layer having a predetermined thickness on the silicon carbide substrate, wherein when a voltage of the silicon carbide substrate is negative, the oxygen ions move close to an interface and perform an oxidation reaction with the silicon carbide, and when the voltage of the silicon carbide substrate is positive, the electrons move close to the interface and perform a reduction reaction with the silicon carbide, removing carbon residue; step four, stopping the introduction of oxygen-containing gas and the reaction completely.
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公开(公告)号：US20190362945A1
公开(公告)日：2019-11-28
申请号：US16224435
申请日：2018-12-18
Inventor： Xinyu LIU , Yidan TANG , Shengkai WANG , Yun BAI , Chengyue YANG
Abstract: A microwave plasma generating device for plasma oxidation of SiC, comprising an outer cavity and a plurality of micro-hole/micro-nano-structured double-coupling resonant cavities disposed in the outer cavity. Each resonant cavity includes a cylindrical cavity. A micro-hole array formed by a plurality of micro-holes is uniformly distributed on a peripheral wall of the cylindrical cavity, a diameter of each of the micro-holes is an odd multiple of wavelength, and an inner wall of the cylindrical cavity has a metal micro-nano structure, the metal micro-nano structure has a periodic dimension of λ/n, where λ is wavelength of an incident wave, and n is refractive index of material of the resonant cavity. The outer cavity is provided with an gas inlet for conveying an oxygen-containing gas into the outer cavity, and the oxygen-containing gas forms an oxygen plasma around the resonant cavities for oxidizing SiC; a stage is disposed under the resonant cavities.
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公开(公告)号：US20190013383A1
公开(公告)日：2019-01-10
申请号：US15759102
申请日：2015-09-10
Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES , ZHUZHOU CRRC TIMES ELECTRIC CO., LTD.
Inventor： Yidan TANG , Huajun SHEN , Yun BAI , Jingtao ZHOU , Chengyue YANG , Xinyu LIU , Chengzhan LI , Guoyou LIU
IPC: H01L29/16 , H01L29/08 , H01L29/06 , H01L29/78 , H01L29/417 , H01L29/423 , H01L29/66 , H01L21/02 , H01L21/04 , H01L21/324 , H01L27/092
Abstract: The present disclosure discloses a self-aligned silicon carbide MOSFET device with an optimized P+ region and a manufacturing method thereof. The self-aligned silicon carbide MOSFET device is formed by a plurality of silicon carbide MOSFET device cells connected in parallel, and these silicon carbide MOSFET device cells are arranged evenly. The silicon carbide MOSFET device cell comprises two source electrodes, one gate electrode, one gate oxide layer, two N+ source regions, two P+ contact regions, two P wells, one N- drift layer, one buffer layer, one N+ substrate, one drain electrode and one isolation dielectric layer. By optimizing the P+ region, the present disclosure forms a good source ohmic contact, reduces the on-resistance, and also shorts the source electrode and the P well to prevent the parasitic transistor effect of the parasitic NPN and PiN, which may take both conduction characteristics and the breakdown characteristics of the device into consideration, and may be applied to a high voltage, high frequency silicon carbide MOSFET device. The self-aligned manufacturing method used in the present disclosure simplifies the process, controls a size of a channel accurately, and may produce a lateral and vertical power MOSFET.
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公开(公告)号：US20170309736A1
公开(公告)日：2017-10-26
申请号：US15368098
申请日：2016-12-02
Inventor： Sen HUANG , Xinyu LIU , Xinhua WANG , Ke WEI , Qilong BAO , Wenwu WANG , Chao ZHAO
IPC: H01L29/778 , H01L29/20 , H01L21/306 , H01L29/15 , H01L29/66 , H01L29/205
CPC classification number: H01L29/7786 , H01L21/30621 , H01L29/1066 , H01L29/155 , H01L29/2003 , H01L29/205 , H01L29/432 , H01L29/66462
Abstract: A GaN-based power electronic device and a method for manufacturing the same is provided. The GaN-based power electronic device comprising a substrate and an epitaxial layer over the substrate. The epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer. The superlattice structure layer is provided over the heterostructure layer, and the P-type cap layer is provided over the superlattice structure layer. By using this electronic device, gate voltage swing and safe gate voltage range of the GaN-based power electronic device manufactured on the basis of the P-type cap layer technique may be further extended, and dynamic characteristics of the device may be improved. Therefore, application process for the GaN-based power electronic device that is based on the P-type cap layer technique will be promoted.
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公开(公告)号：US20170125571A1
公开(公告)日：2017-05-04
申请号：US15333674
申请日：2016-10-25
Inventor： Sen HUANG , Xinyu LIU , Xinhua WANG , Ke WEI
IPC: H01L29/778 , H01L29/47 , H01L21/02 , H01L29/66 , H01L29/20
CPC classification number: H01L29/7787 , H01L21/0217 , H01L21/02274 , H01L21/0228 , H01L21/0254 , H01L21/0262 , H01L21/02636 , H01L23/291 , H01L23/3171 , H01L29/2003 , H01L29/475 , H01L29/66462 , H01L29/7786
Abstract: A GaN-based enhancement-mode power electronic device and a method for manufacturing the same. The GaN-based enhancement-mode power electronic device comprises: a substrate; a thin barrier Al(In,Ga)N/GaN heterostructure formed on the substrate; a gate, a source, and a drain formed on the thin barrier Al(In,Ga)N/GaN heterostructure. An AlN or SiNx passivation layer is formed on access regions between the gate and the source and between the gate and the drain, respectively, such that two dimensional electron gas is recovered in channels of the thin barrier Al(In,Ga)N/GaN heterostructure below the MN passivation layer by utilizing the MN passivation layer having polarization characteristics, or by using the SiNx passivation layer with positive fixed bulk/interface charges, so as to reduce on-resistance of the device and inhibit high-voltage current collapse in the device.
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