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    Reset dominant level-shift high side MOS driver
    2.
    发明专利
    Reset dominant level-shift high side MOS driver 未知

    公开(公告)号：GB2291294A

    公开(公告)日：1996-01-17

    申请号：GB9514053

    申请日：1995-07-10

    Applicant: INT RECTIFIER CORP

    Inventor： TAM DAVID ,  CHOI CHONGWOOK CHRIS

    IPC: H03K19/003 ,  H03K17/16 ,  H03K19/0185 ,  H03K19/0944

    Abstract: The logic circuit of the level shifting circuit of a high side MOS gate device is made reset dominant to make the circuit immune to noise glitches. The reset dominance is obtained by causing a reset signal to be produced at a wider range of high side floating supply offset voltage than that at which the set signal can be produced to prevent the chance of a set when the high side power MOSFET should be off. The reset dominance is obtained by increasing the size of the reset voltage dropping resistor 91 or by adjusting the input threshold of the circuit 94 reading the set and reset voltage dropping resistors.

    Circuit providing dv/dt immunity
    5.
    发明专利
    Circuit providing dv/dt immunity 未知

    公开(公告)号：GB2244400A

    公开(公告)日：1991-11-27

    申请号：GB9110324

    申请日：1991-05-13

    Applicant: INT RECTIFIER CORP

    Inventor： KINZER DANIEL M ,  TAM DAVID

    IPC: H02M1/08 ,  G01R29/027 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003

    Abstract: A pulse filter (93) is connected between a high voltage level shift circuit (59) which produces output pulses in a pattern determined by an input logic circuit (50-58) and the high side output circuit (94-101) which controls the production of power MOSFET or IGBT gate signals or the like. The pulse filter (93) immunizes the circuit against false operation duo to the fast dv/dt transients. The pulse filter (93) includes inverters for squaring an input signal and a CR delay element for increasing the rise time of the pulse so that pulses derived from transients are too small to drive the following stage and hence blocked. A pulse generator (80) derives set and reset pulses from the logic level of inputs (at 10, 11) and level shifted (at 59). Elements (61-70) relate to low voltage switching circuit. High voltage switching circuit (100, 101) drive power MOSFET's or IGBTs in a load circuit. Detectors (102, 70) prevent operation when supply voltage is low.

    Reset dominant level-shift circuit for noise immunity
    6.
    发明专利
    Reset dominant level-shift circuit for noise immunity 未知

    公开(公告)号：GB2291294B

    公开(公告)日：1998-11-18

    申请号：GB9514053

    申请日：1995-07-10

    Applicant: INT RECTIFIER CORP

    Inventor： TAM DAVID ,  CHOI CHONGWOOK CHRIS

    IPC: H03K19/003 ,  H03K17/16 ,  H03K19/0185 ,  H03K19/0944

    Abstract: The logic circuit of the level shifting circuit of a high side MOS gate device is made reset dominant to make the circuit immune to noise glitches. The reset dominance is obtained by causing a reset signal to be produced at a wider range of high side floating supply offset voltage than that at which the set signal can be produced to prevent the chance of a set when the high side power MOSFET should be off. The reset dominance is obtained by increasing the size of the reset voltage dropping resistor or by adjusting the input threshold of the circuit reading the set and reset voltage dropping resistors.

    Half bridge driver with biassing of intrinsic diodes associated with the output transistors to eliminate effects of negative voltage spikes
    7.
    发明专利
    Half bridge driver with biassing of intrinsic diodes associated with the output transistors to eliminate effects of negative voltage spikes 未知

    公开(公告)号：GB2300532A

    公开(公告)日：1996-11-06

    申请号：GB9609472

    申请日：1996-05-07

    Applicant: INT RECTIFIER CORP

    Inventor： CHOI CHONGWOOK CHRIS ,  TAM DAVID

    IPC: H01L21/8234 ,  H01L27/088 ,  H02M1/08 ,  H03F1/52 ,  H03K17/06 ,  H03K17/687

    Abstract: A method and circuit for driving power transistors arranged in series in a half bridge configuration allowing for excessive negative swing of an output node between the transistors in the half bridge configuration. The series transistors are connected between a first voltage source and a common potential. A second voltage reference source is also provided. A terminal is connected to a common point coupled to anodes of intrinsic diodes of driver circuits for the power transistors. The second voltage source is connected between the common potential and the terminal so as to shift the level of the common point such that the intrinsic diodes will not forward bias due to negative output node transients generated by diode forward recovery and stray inductances. The circuit of the invention can also be incorporated in an integrated circuit including a single chip, e.g., a silicon chip.

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