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    명확화 없는 비순차 LOAD STORE 큐
    1.
    发明公开
    명확화 없는 비순차 LOAD STORE 큐 审中-公开
    LOAD STORE无损失的无序加载存储队列

    公开(公告)号：KR20180008870A

    公开(公告)日：2018-01-24

    申请号：KR20187000693

    申请日：2013-06-14

    Applicant: INTEL CORP

    Inventor： ABDALLAH MOHAMMAD

    IPC: G06F9/38

    CPC classification number: G06F9/30043 ,  G06F9/30032 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3855 ,  G06F9/3857

    Abstract: 프로세서에서, 명확화없는비순차 load store 큐방법이개시된다. 이방법은복수의비동기코어들에의해액세스될수 있는메모리자원을구현하는단계; store 회수버퍼를구현하는단계 - store 큐로부터의 store들은원래의프로그램순서로 store 회수버퍼에엔트리들을가짐 -; 및 load 큐로부터의후속하는 load의디스패치시에, 주소일치가있는지 store 회수버퍼를검색하는단계를포함한다. 이방법은복수의주소일치들이있는경우에, 제1 일치가있는지 store 회수버퍼를스캔하는것에의해정확한포워딩엔트리를위치확인하는단계; 및제1 일치로부터의데이터를후속하는 load로포워딩하는단계를추가로포함한다.

    Abstract translation: 在一个处理器中，一个无歧义的消除乱序加载存储队列方法。 该方法包括实现可由多个异步核心访问的存储器资源; 实现商店退休缓冲区，其中来自商店队列的商店具有原始节目顺序的商店退休缓冲区中的条目; 并且在从加载队列分派后续加载时，在商店退休缓冲区中搜索地址匹配。 该方法进一步包括在存在多个地址匹配的情况下，通过针对第一匹配扫描商店引退缓冲器来定位正确的转发条目; 并将数据从第一个匹配转发到后续加载。

    Method and device for performing selection operation
    2.
    发明专利
    Method and device for performing selection operation 有权
    用于执行选择操作的方法和装置

    公开(公告)号：JP2008140372A

    公开(公告)日：2008-06-19

    申请号：JP2007245615

    申请日：2007-09-21

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： ZOHAR ,  ABDALLAH MOHAMMAD ,  SABANIN BORIS ,  SECONI MARK

    IPC: G06F9/30 ,  G06F9/305 ,  G06F9/38

    CPC classification number: G06F9/30112 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30138 ,  G06F9/30185

    Abstract: PROBLEM TO BE SOLVED: To provide a command for performing a selection operation for packed data and unpacked data. SOLUTION: First packed data in a source operand and second packed data in a destination operand are stored in a memory connected to a processor. The processor selects the first packed data if the control bit of the source operand is set to "1", and stores it in the destination operand. If the control bit is not set to "1", the processor keeps the data in the destination operand. The final value of the destination operand is stored in the memory. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供用于执行打包数据和未打包数据的选择操作的命令。 解决方案：目的操作数中的源操作数和第二打包数据中的第一打包数据存储在连接到处理器的存储器中。 如果源操作数的控制位设置为“1”，则处理器选择第一打包数据，并将其存储在目标操作数中。 如果控制位未设置为“1”，则处理器将数据保存在目标操作数中。 目标操作数的最终值存储在内存中。 版权所有（C）2008，JPO＆INPIT

    Method and device for performing selection operation
    3.
    发明专利
    Method and device for performing selection operation 有权
    用于执行选择操作的方法和装置

    公开(公告)号：JP2012119009A

    公开(公告)日：2012-06-21

    申请号：JP2012015834

    申请日：2012-01-27

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： ZOHAR ,  ABDALLAH MOHAMMAD ,  SABANIN BORIS ,  SECONI MARK

    IPC: G06F9/30

    CPC classification number: G06F9/30112 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30138 ,  G06F9/30185

    Abstract: PROBLEM TO BE SOLVED: To provide a method and a device including, in a processor, a command for performing a selection operation for packed data and non-packed data.SOLUTION: A memory is connected to a processor. First packed data in a source operand and second packed data in a destination operand are stored in the memory. The processor selects the first packed data if a control bit of the source operand is set to "1", and stores the first packed data in the destination operand. If the control bit is not set to "1", the processor keeps the data in the destination operand. A final value of the destination operand is stored in the memory.

    Abstract translation: 要解决的问题：提供一种在处理器中包括用于对打包数据和非打包数据执行选择操作的命令的方法和装置。

    解决方案：存储器连接到处理器。 源操作数中的第一打包数据和目的操作数中的第二打包数据存储在存储器中。 如果源操作数的控制位被设置为“1”，则处理器选择第一打包数据，并将第一打包数据存储在目的地操作数中。 如果控制位未设置为“1”，则处理器将数据保存在目标操作数中。 目的地操作数的最终值存储在存储器中。 版权所有（C）2012，JPO＆INPIT

    4.
    发明专利
    未知

    公开(公告)号：DE112007002146T5

    公开(公告)日：2009-07-02

    申请号：DE112007002146

    申请日：2007-09-20

    Applicant: INTEL CORP

    Inventor： ZOHAR RONEN ,  ABDALLAH MOHAMMAD ,  SABANIN BORIS ,  SECONI MARK

    IPC: G06F9/345 ,  G06F9/06 ,  G06F9/30

    Abstract: A method and apparatus for including in a processor instructions for performing select operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein first packed data in a source operand and a second packed data in a destination operand. The processor selects the first packed data if the control bit for the source operand is set to "1" and stores the data into the destination operand. Otherwise, the processor keeps the data in the destination operand. The final value of the destination operand is stored in memory.

    5.
    发明专利
    未知

    公开(公告)号：BR9901145A

    公开(公告)日：1999-12-21

    申请号：BR9901145

    申请日：1999-03-31

    Applicant: INTEL CORP

    Inventor： ROUSSEL PATRICE ,  CHENNUPATY SRINIVAS ,  CRANFORD MIKE ,  ABDALLAH MOHAMMAD ,  COKE JIM ,  KONG KATHERINE

    IPC: G06F9/30 ,  G06F9/315 ,  G06F9/38

    Abstract: An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.

    System and method for prefetching data into a cache based on miss distance
    7.
    发明专利
    System and method for prefetching data into a cache based on miss distance 未知

    公开(公告)号：HK1064170A1

    公开(公告)日：2005-01-21

    申请号：HK04106821

    申请日：2004-09-08

    Applicant: INTEL CORP

    Inventor： ABDALLAH MOHAMMAD ,  AL-DAJANI KHALID

    IPC: G06F9/38 ,  G06F12/08 ,  G06F

    Abstract: A prefetcher to prefetch data for an instruction based on the distance between cache misses caused by the instruction. In an embodiment, the prefetcher includes a memory to store a prefetch table that contains one or more entries that include the distance between cache misses caused by an instruction. In a further embodiment, the addresses of data elements prefetched are determined based on the distance between cache misses recorded in the prefetch table for the instruction.

    System and method for prefetching data into a cache based on miss distance
    8.
    发明专利
    System and method for prefetching data into a cache based on miss distance 未知

    公开(公告)号：AU2002241682A1

    公开(公告)日：2002-07-16

    申请号：AU2002241682

    申请日：2001-12-18

    Applicant: INTEL CORP

    Inventor： ABDALLAH MOHAMMAD ,  AL-DAJANI KHALID

    IPC: G06F9/38 ,  G06F12/08

    Abstract: A prefetcher to prefetch data for an instruction based on the distance between cache misses caused by the instruction. In an embodiment, the prefetcher includes a memory to store a prefetch table that contains one or more entries that include the distance between cache misses caused by an instruction. In a further embodiment, the addresses of data elements prefetched are determined based on the distance between cache misses recorded in the prefetch table for the instruction.

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