公开(公告)号：JP2008077663A

公开(公告)日：2008-04-03

申请号：JP2007244076

申请日：2007-09-20

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： ZOHAR RONEN ,  SECONI MARK ,  PARTHASARATHY RAJESH ,  CHENNUPATY SRINIVAS ,  BUXTON MARK ,  DESYLVA CHUCK

IPC: G06F17/16 ,  G06F9/30

CPC classification number: G06F17/10 ,  G06F7/48 ,  G06F7/5443 ,  G06F9/3001

Abstract: PROBLEM TO BE SOLVED: To provide a method, an apparatus, and a programming means for significantly decreasing the number of instructions required for a dot-product operation. SOLUTION: In one embodiment, the apparatus comprises an execution resource for executing a first instruction decoded to one micro operation. In response to the first instruction, the execution resource calculates the dot product of at least two source operands for a specific data type including an integer and a floating point, and stores the result value in the same register or memory location as one of the source operands. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于显着减少点产品操作所需指令数量的方法，装置和编程装置。 解决方案：在一个实施例中，该装置包括用于执行解码为一个微操作的第一指令的执行资源。 响应于第一指令，执行资源计算用于包括整数和浮点的特定数据类型的至少两个源操作数的点乘积，并将结果值存储在与源中的一个相同的寄存器或存储器位置 操作数。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：DE112007002146T5

公开(公告)日：2009-07-02

申请号：DE112007002146

申请日：2007-09-20

Applicant: INTEL CORP

Inventor： ZOHAR RONEN ,  ABDALLAH MOHAMMAD ,  SABANIN BORIS ,  SECONI MARK

IPC: G06F9/345 ,  G06F9/06 ,  G06F9/30

Abstract: A method and apparatus for including in a processor instructions for performing select operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein first packed data in a source operand and a second packed data in a destination operand. The processor selects the first packed data if the control bit for the source operand is set to "1" and stores the data into the destination operand. Otherwise, the processor keeps the data in the destination operand. The final value of the destination operand is stored in memory.

公开(公告)号：DE112007002101T5

公开(公告)日：2009-07-09

申请号：DE112007002101

申请日：2007-09-20

Applicant: INTEL CORP

Inventor： ZOHAR RONEN ,  SECONI MARK ,  PARTHASARATHY RAJESH ,  CHENNUPATY SRINIVAS ,  BUXTON MARK ,  DESYLVA CHUCK ,  ABDALLAH MOHAMMAD A

IPC: G06F9/30 ,  G06F7/00 ,  G06F9/06

Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.

公开(公告)号：ES2905697T3

公开(公告)日：2022-04-11

申请号：ES19183504

申请日：2019-06-28

Applicant: INTEL CORP

Inventor： BAUM DAN ,  ZOHAR RONEN ,  MISHRA ASIT ,  SURTI PRASOONKUMAR ,  ELMOUSTAPHA OULD-AHMED-VALL ,  HUGHES CHRISTOPHER ,  HEINECKE ALEXANDER

IPC: G06F9/30

Abstract: Un procesador (1390) que comprende: una circuitería de descodificación (1303) para descodificar una instrucción, incluyendo la instrucción un primer campo para identificar una ubicación de un vector de origen, un segundo campo para identificar una ubicación de un vector de destino y un código de operación para indicar a una circuitería de ejecución (1311) que ejecute la instrucción descodificada para clasificar valores del vector de origen y almacenar un resultado de la clasificación en el vector de destino generando, por cada elemento del vector de origen, un valor de índice usando una o más comparaciones del propio elemento y con otros elementos de datos del vector de origen, y permutando los valores de los elementos del vector de origen basándose en los valores de índice para los elementos; y una circuitería de ejecución (1311) para ejecutar la instrucción descodificada como es indicado por el código de operación, en donde la circuitería de ejecución (1311) comprende una circuitería de operaciones matriciales (2301) para generar el índice y una circuitería de procesamiento de vectores (2303) para permutar y almacenar los valores de los elementos basándose en los valores de índice.

公开(公告)号：DE102007045187A1

公开(公告)日：2008-04-30

申请号：DE102007045187

申请日：2007-09-21

Applicant: INTEL CORP

Inventor： KAPOOR RAJIV ,  ZOHAR RONEN ,  BUXTON MARK ,  SPERBER ZEEV ,  GOTTLIEB KOBY

IPC: G06F7/499 ,  G06F7/57

Abstract: A method and apparatus for including in processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

公开(公告)号：PL3608776T3

公开(公告)日：2022-04-04

申请号：PL19183504

申请日：2019-06-28

Applicant: INTEL CORP

Inventor： BAUM DAN ,  ZOHAR RONEN ,  MISHRA ASIT ,  SURTI PRASOONKUMAR ,  ELMOUSTAPHA OULD-AHMED-VALL ,  HUGHES CHRISTOPHER ,  HEINECKE ALEXANDER

IPC: G06F9/30

公开(公告)号：DE112007001989B4

公开(公告)日：2019-04-18

申请号：DE112007001989

申请日：2007-09-21

Applicant: INTEL CORP

Inventor： ZOHAR RONEN ,  STORY SHANE

IPC: G06F7/38 ,  G06F7/499 ,  G06F9/302

Abstract: Verfahren, umfassend:Empfangen (110) einer Nutzerebenenrundungsanweisung einer Befehlssatzarchitektur (ISA) und eines Immediate-Wertes in einem Prozessor;Bestimmen (115), ob ein in dem Immediate-Wert enthaltener Rundungsmodusübersteuerungsindikator aktiv ist; undwenn ja, Erhalten eines in dem Immediate-Wert enthaltenen Rundungsmodusfeldes, wobei das Rundungsmodusfeld vom Übersteuerungsindikator getrennt ist, und um einen von einer Mehrzahl von Rundungsmodi anzuzeigen;Ausführen (130) einer Rundungsoperation an einem Quelloperanden in einer Gleitkommaeinheit des Prozessors entsprechend der Nutzerebenenrundungsanweisung und gemäß einem Rundungsmodus im in dem Immediate-Wert enthaltenen Rundungsmodusfeld; undUnterdrücken einer Präzisionsausnahme, die aus der Rundungsoperation resultiert, wenn ein vom Rundungsmodusübersteuerungsindikator und dem Rundungsmodusfeld getrennter Präzisionsunterdrückungsindikator, der in dem Immediate-Wert enthalten ist, aktiv ist und, falls der Präzisionsunterdrückungsindikator nicht aktiv ist, und während der Rundungsoperation die Präzisionsausnahme aufgetreten ist, Setzen eines Präzisionsausnahme-Flags in einem Statusregister des Prozessors.

公开(公告)号：DE112007003786A5

公开(公告)日：2012-11-15

申请号：DE112007003786

申请日：2007-09-20

Applicant: INTEL CORP

Inventor： ABDALLAH MOHAMMAD ,  SECONI MARK ,  SABANIN BORIS ,  ZOHAR RONEN

IPC: G06F9/345 ,  G06F9/06 ,  G06F9/30

公开(公告)号：DE112007001989T5

公开(公告)日：2009-06-18

申请号：DE112007001989

申请日：2007-09-21

Applicant: INTEL CORP

Inventor： ZOHAR RONEN ,  STORY SHANE

IPC: G06F7/38 ,  G06F9/28 ,  G06F9/30

Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.