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    Performing aes encryption or decryption in multiple modes with single instruction
    2.
    发明专利
    Performing aes encryption or decryption in multiple modes with single instruction 有权
    在单个指令的多种模式下执行AES加密或解码

    公开(公告)号：JP2008283672A

    公开(公告)日：2008-11-20

    申请号：JP2008064272

    申请日：2008-03-13

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： DIXON MARTIN ,  CHENNUPATY SRINIVAS ,  GUERON SHAY

    IPC: H04L9/10 ,  G06F9/30 ,  G09C1/00

    CPC classification number: H04L9/0631 ,  G06F9/30007 ,  H04L9/0637 ,  H04L9/28 ,  H04L2209/12

    Abstract: PROBLEM TO BE SOLVED: To provide an Advanced Encryption Standard (AES) encryption instruction, having two operands, encrypting/decrypting data in at least two modes. SOLUTION: The present invention relates to a machine-readable medium which may have stored thereon an instruction, which, when executed by a machine, causes the machine to perform a method. The method may include combining a first operand of the instruction and a second operand of the instruction to produce a result. The result may be encrypted using a key in accordance with an Advanced Encryption Standard (AES) algorithm to produce an encrypted result. The method may also include placing the encrypted result in a location of the first operand of the instruction. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供具有两个操作数的高级加密标准（AES）加密指令，以至少两种模式对数据进行加密/解密。 解决方案：本发明涉及一种机器可读介质，其可以存储有指令，当由机器执行时，该指令使机器执行方法。 该方法可以包括组合指令的第一操作数和指令的第二操作数以产生结果。 可以使用根据高级加密标准（AES）算法的密钥来加密结果以产生加密结果。 该方法还可以包括将加密结果放置在指令的第一操作数的位置。 版权所有（C）2009，JPO＆INPIT

    Instruction and logic for performing dot-product operation
    4.
    发明专利
    Instruction and logic for performing dot-product operation 有权
    执行产品操作的指导和逻辑

    公开(公告)号：JP2008077663A

    公开(公告)日：2008-04-03

    申请号：JP2007244076

    申请日：2007-09-20

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： ZOHAR RONEN ,  SECONI MARK ,  PARTHASARATHY RAJESH ,  CHENNUPATY SRINIVAS ,  BUXTON MARK ,  DESYLVA CHUCK

    IPC: G06F17/16 ,  G06F9/30

    CPC classification number: G06F17/10 ,  G06F7/48 ,  G06F7/5443 ,  G06F9/3001

    Abstract: PROBLEM TO BE SOLVED: To provide a method, an apparatus, and a programming means for significantly decreasing the number of instructions required for a dot-product operation. SOLUTION: In one embodiment, the apparatus comprises an execution resource for executing a first instruction decoded to one micro operation. In response to the first instruction, the execution resource calculates the dot product of at least two source operands for a specific data type including an integer and a floating point, and stores the result value in the same register or memory location as one of the source operands. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于显着减少点产品操作所需指令数量的方法，装置和编程装置。 解决方案：在一个实施例中，该装置包括用于执行解码为一个微操作的第一指令的执行资源。 响应于第一指令，执行资源计算用于包括整数和浮点的特定数据类型的至少两个源操作数的点乘积，并将结果值存储在与源中的一个相同的寄存器或存储器位置 操作数。 版权所有（C）2008，JPO＆INPIT

    Performing AES encryption or decryption in multiple modes with a single instruction
    7.
    发明专利
    Performing AES encryption or decryption in multiple modes with a single instruction 未知

    公开(公告)号：GB2447563A

    公开(公告)日：2008-09-17

    申请号：GB0804870

    申请日：2008-03-14

    Applicant: INTEL CORP

    Inventor： DIXON MARTIN ,  CHENNUPATY SRINIVAS ,  GUERON SHAY

    IPC: H04L9/06 ,  G06F21/00

    Abstract: The invention relates to instructions for a causing a processor to perform Advanced Encryption Standard (AES) encryption/decryption. The instructions can be used to perform different modes of AES encryption/decryption including Cipher-Block Chaining (CBC) mode, Electronic Codebook (ECB) mode and Counter (CTR) mode. An AESENCRYPT instruction for performing encryption comprises two operands, one of which supplies the plaintext to be encrypted. One scheme to determine in which mode (ECB, CBC etc) the instruction operates is to combine the two operands, e.g. XORing, before encrypting the result with an encryption key. If only one input is desired, as is the case for ECB mode, then the other operand may be set to zero (fig. 3). When used in CBC mode the other operand provides the so-called "old" ciphertext from the prior encrypted block, which is XORed with the plaintext before encryption (fig. 5). In CTR mode (fig. 8) one of the operands supplies the counter value and the other operand provides the plaintext. A single instruction for decryption, AESDECRYPT, is also disclosed.

    8.
    发明专利
    未知

    公开(公告)号：BR9901145A

    公开(公告)日：1999-12-21

    申请号：BR9901145

    申请日：1999-03-31

    Applicant: INTEL CORP

    Inventor： ROUSSEL PATRICE ,  CHENNUPATY SRINIVAS ,  CRANFORD MIKE ,  ABDALLAH MOHAMMAD ,  COKE JIM ,  KONG KATHERINE

    IPC: G06F9/30 ,  G06F9/315 ,  G06F9/38

    Abstract: An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.

    9.
    发明专利
    未知

    公开(公告)号：BR9901215B1

    公开(公告)日：2013-12-24

    申请号：BR9901215

    申请日：1999-03-30

    Applicant: INTEL CORP

    Inventor： CHENNUPATY SRINIVAS ,  HACKING LANCE ,  HUFF THOMAS ,  ROUSSEL PATRICE L ,  THAKKAR SHREEKANT S

    IPC: G06F9/318

    Abstract: The present invention discloses a method and apparatus for encoding an instruction in an instruction set which uses a prefix code to qualify an existing opcode of an existing instruction. An opcode and an escape code are selected. The escape code is selected such that it is different from the prefix code and the existing opcode. The opcode, the escape code, and the prefix code are combined to generate an instruction code which uniquely represents the operation performed by the instruction.

    10.
    发明专利
    未知

    公开(公告)号：BRPI0717068A2

    公开(公告)日：2013-09-24

    申请号：BRPI0717068

    申请日：2007-09-21

    Applicant: INTEL CORP

    Inventor： JULIER MICHAEL A ,  GRAY JEFFREY D ,  CHENNUPATY SRINIVAS ,  MIRKES SEAN P ,  SECONI MARK P

    IPC: G06F9/06

    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

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