公开(公告)号：WO2007078538A3

公开(公告)日：2007-08-30

申请号：PCT/US2006046499

申请日：2006-12-05

Applicant: INTEL CORP ,  ADL-TABATABAI ALI-REZA ,  SAHA BRATIN ,  HUDSON RICHARD L ,  AKKARY HAITHAM ,  RAJWAR RAVI

Inventor： ADL-TABATABAI ALI-REZA ,  SAHA BRATIN ,  HUDSON RICHARD L ,  AKKARY HAITHAM ,  RAJWAR RAVI

IPC: G06F9/52

CPC classification number: G06F9/467 ,  G06F12/0815 ,  G06F2212/507

Abstract: Provided is a method, system, and program for coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions. A hardware transaction executing in hardware transactional memory initiates a request to access a memory location. A fault is returned to the hardware transaction request in response to an operation by one software transaction executing in a software transactional memory.

Abstract translation: 提供了用于协调对硬件事务存储器事务和软件事务存储器事务的存储器位置的访问的方法，系统和程序。 在硬件事务存储器中执行的硬件事务启动访问存储器位置的请求。 响应于在软件事务存储器中执行的一个软件事务的操作，错误返回到硬件事务请求。

公开(公告)号：WO2006039201A3

公开(公告)日：2006-11-16

申请号：PCT/US2005034145

申请日：2005-09-21

Applicant: INTEL CORP ,  AKKARY HAITHAM ,  RAJWAR RAVI ,  SRINIVASAN SRIKANTH

Inventor： AKKARY HAITHAM ,  RAJWAR RAVI ,  SRINIVASAN SRIKANTH

IPC: G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3863

Abstract: Embodiments of the present invention relate to a system and method for comparatively increasing processor throughput and relieving pressure on the processor's scheduler and register file by diverting instructions dependent on long-latency operations from a flow of the processor pipeline and re-introducing them into the flow when the long-latency operations are completed. In this way, the instructions do not tie up resources and overall instruction throughput in the pipeline is comparatively increased.

Abstract translation: 本发明的实施例涉及用于通过从处理器流水线的流转移取决于长等待时间操作的指令并将其重新引入流中来相对增加处理器吞吐量并减轻处理器的调度器和寄存器文件上的压力的系统和方法 当长时间延迟操作完成时。 这样，指令不会占用资源，并且管道中的整体指令吞吐量相对增加。

公开(公告)号：WO03003196A2

公开(公告)日：2003-01-09

申请号：PCT/US0219101

申请日：2002-06-14

Applicant: INTEL CORP

Inventor： AKKARY HAITHAM ,  HILY SEBASTIEN

IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/3851 ,  G06F9/30072 ,  G06F9/3013 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857

Abstract: A device is presented including a first processor and a second processor. A number of memory devices are connected to the first processor and the second processor. A register buffer is connected to the first processor and the second processor. A trace buffer is connected to the first processor and the second processor. A number of memory instruction buffers are connected to the first processor and the second processor. The first processor and the second processor perform single threaded applications using multithreading resources. A method is also presented where a first thread is executed from a second processor. The first thread is also executed from a second processor as directed by the first processor. The second processor executes instructions ahead of the first processor.

Abstract translation: 呈现包括第一处理器和第二处理器的设备。 多个存储设备连接到第一处理器和第二处理器。 寄存器缓冲器连接到第一处理器和第二处理器。 跟踪缓冲区连接到第一个处理器和第二个处理器。 多个存储器指令缓冲器连接到第一处理器和第二处理器。 第一个处理器和第二个处理器使用多线程资源执行单线程应用程序。 还提出了一种方法，其中从第二处理器执行第一线程。 第一个线程也由第一个处理器控制的第二个处理器执行。 第二个处理器在第一个处理器之前执行指令。

公开(公告)号：EP1040423A4

公开(公告)日：2002-07-17

申请号：EP98963874

申请日：1998-12-11

Applicant: INTEL CORP

Inventor： AKKARY HAITHAM

IPC: G06F9/38

CPC classification number: G06F9/3834 ,  G06F9/3851

Abstract: In one embodiment of the invention, a processor includes a memory order buffer (MOB) (178) including load buffers (182) and store buffers (184), wherein the MOB orders load and store instructions so as to maintain data coherency between load and store instructions in different threads, wherein at least one of the threads is dependent on at least another one of the threads. In another embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least another one of the threads, the execution pipeline including a memory order buffer that orders load and store instructions. The processor also includes detection circuitry to detect speculation errors associated with load instructions in a load buffer.

公开(公告)号：EP1068570A4

公开(公告)日：2002-07-17

申请号：EP98963903

申请日：1998-12-11

Applicant: INTEL CORP

Inventor： AKKARY HAITHAM ,  CHOW KINGSUM

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/40

CPC classification number: G06F9/3842 ,  G06F9/3013 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3863

Abstract: In one embodiment of the invention, a processor (50) includes an execution pipeline (108) to concurrently execute at least portions of threads T1-T4, wherein at least one of the threads is dependant on at least another one of the threads. The processor (50) also includes detection circuitry to detect speculation errors in the execution of the threads T1-T4. In another embodiment, the processor (50) includes thread management logic (124) to control dynamic creation of threads from a program (112A).

公开(公告)号：EP1040421A4

公开(公告)日：2002-07-17

申请号：EP98963873

申请日：1998-12-11

Applicant: INTEL CORP

Inventor： AKKARY HAITHAM

IPC: G06F9/38 ,  G06F11/14 ,  G06F11/28 ,  G06F9/40

CPC classification number: G06F9/3863 ,  G06F9/3842 ,  G06F11/1407

Abstract: In one embodiment of the invention, a processor (10) includes and execution pipeline to execute instructions, wherein at least some of the instructions are executed speculatively. The processor also includes a trace buffer (114) outside the execution pipeline to hold the instructions, and wherein instructions that are associated with speculation errors are replayed in the execution pipeline to execute instructions, wherein at least some of the instructions are executed speculatively. The processor also includes a trace buffer outside the execution pipeline to hold instructions and results of the execution of the instructions, wherein at least some of the instructions are subject to an initial retirement following execution in the pipeline, but remain in the trace buffer until a final retirement (134).

公开(公告)号：GB2447200B

公开(公告)日：2011-06-22

申请号：GB0812727

申请日：2007-03-20

Applicant: INTEL CORP

Inventor： RAJWAR RAVI ,  AKKARY HAITHAM ,  LAI KONRAD

IPC: G06F9/46 ,  G06F9/44

Abstract: Methods and apparatus to provide transactional memory execution in out-of-order processors are described. In one embodiment, a stored value corresponds to the number of transactional memory access requests that are uncommitted. The stored value may be used to provide nested recovery in case of an error, fault, etc. in accordance with a described embodiment.

公开(公告)号：HK1062056A1

公开(公告)日：2004-10-15

申请号：HK04104979

申请日：2004-07-08

Applicant: INTEL CORP

Inventor： AKKARY HAITHAM ,  HILY SEBASTIEN

IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F

Abstract: A device is presented including a first processor and a second processor. A number of memory devices are connected to the first processor and the second processor. A register buffer is connected to the first processor and the second processor. A trace buffer is connected to the first processor and the second processor. A number of memory instruction buffers are connected to the first processor and the second processor. The first processor and the second processor perform single threaded applications using multithreading resources. A method is also presented where a first thread is executed from a first processor. The first thread is also executed from a second processor as directed by the first processor. The second processor executes instructions ahead of the first processor.

公开(公告)号：GB2393297A

公开(公告)日：2004-03-24

申请号：GB0329899

申请日：2002-06-14

Applicant: INTEL CORP

Inventor： AKKARY HAITHAM ,  HILY SEBASTIEN

IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A device is presented including a first processor and a second processor. A number of memory devices are connected to the first processor and the second processor. A register buffer is connected to the first processor and the second processor. A trace buffer is connected to the first processor and the second processor. A number of memory instruction buffers are connected to the first processor and the second processor. The first processor and the second processor perform single threaded applications using multithreading resources. A method is also presented where a first thread is executed from a second processor. The first thread is also executed from a second processor as directed by the first processor. The second processor executes instructions ahead of the first processor.

公开(公告)号：BR9813650A

公开(公告)日：2000-10-03

申请号：BR9813650

申请日：1998-12-11

Applicant: INTEL CORP

Inventor： AKKARY HAITHAM ,  CHOW KINGSUM

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/30 ,  G06F9/40

Abstract: In one embodiment, a processor includes thread management logic including a thread predictor having state machines to indicate whether thread creation opportunities should be taken or not taken. The processor includes a predictor training mechanism to receive retired instructions and to identify potential threads from the retired instructions and to determine whether a potential thread of interest meets a test of thread goodness, and if the test is met, one of the state machines that is associated with the potential thread of interest is updated in a take direction, and if the test is not met, the state machine is updated in a not take direction. The thread management logic may control creation of an actual thread and may further include reset logic to control whether the actual thread is reset and wherein if the actual thread is reset, one of the state machines associated with the actual thread is updated in a not take direction. The final retirement logic may control whether the actual thread is retired, and wherein if the actual thread is retired, the state machine associated with the actual thread is updated in a take direction. The circuitry may be used in connection with a multi-threading processor that detects speculation errors involving thread dependencies in execution of the actual threads and re-executes instructions associated with the speculation errors from trace buffers outside an execution pipeline.